DA9021 datasheet(63/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

63 of 142

processed. If a domain contains at least one supply with an assigned preset, the power domain

status indicator (PWR1_UP, PWR_UP) will not be released. Otherwise the indicator will be released

before the first supply of a power domain is disabled.

If powering down was initiated from releasing PWR_EN1 the sequencer will stop to modify the

supplies where the domain pointer POWER_END reached. If PWR_EN was disabled the domain

POWER1 will be powered down followed by POWER until the sequencer reaches pointer

SYSTEM_END. If SYS_EN was disabled the sequencer will process all IDs lower than the actual

pointer position down to step 0.

If the low power mode was initiated by asserting the control register DEEP_SLEEP the sequencer

will first power down POWER1 and POWER, then continue with SYSTEM and stop when pointer

PART_DOWN has been reached (PART_DOWN has to point into domain SYSTEM). If SYS_EN was

disabled the sequencer will process all IDs lower than the actual pointer position down to step 0

(ignoring the PART_DOWN pointer).

The sequencer asserts the E_SEQ_RDY interrupt on reaching the target pointer position. During

processing step 0 all supplies (except LDOCORE) can be set to their OTP default state (if bit

DEF_SUPPLY of step 0 is asserted), but the voltage levels are unchanged. Due to the risk of in-rush

currents on the battery the default enable of more than a single supply at step 0 is not recommended.

Asserting control register bit SHUTDOWN will first power down to step 0 and then force DA9021/22

to RESET mode. DA9021/22 features (for example the OUT_32K output buffer or an auto ADC

measurement) can be disabled temporarily in POWERDOWN mode via register PD_DIS. The timing

for processing PD_DIS can be defined by the placement of PD_DIS inside the sequence. Features

asserted in PD_DIS are re-enabled when PD_DIS is processed during the next power-up sequence.

If the READY signal is enabled, it will be asserted during processing the IDs for powering down.

NOTE

Any reconfiguration of supplies from the host in ACTIVE mode will not affect the domain status indicators

(SYS_UP, and PWR_UP). During sequencing (indicated from DA9021/22 via signal READY or the E_SEQ_RDY

interrupt) the host is not allowed to send additional power mode transition requests (via power manger interface

or power domain enable lines).

A CONDITIONAL mode transition can be achieved using ID WAIT_STEP. If pointing into the

sequence the progress of an initiated mode transition can be synchronised, for example with the

state of a host that is indicated via a signal connected to GPI10. Via GPIO10_ MODE a security time-

out of 500 ms can be selected, that will trigger a power down to RESET mode (including the

assertion of WAIT_SHUT inside register FAULT_LOG) if E_GPI10 was not asserted until then.

NOTE

In the case of a shutdown sequence towards RESET mode (or POWERDOWN from fault condition) any waiting

from ID WAIT_STEP will be skipped.

When powering up from NO_POWER mode ID WAIT_STEP can alternatively be used as a

configurable delay to allow the 32 kHz oscillator to stabilise before the TTL signal is provided at the

OUT_32K output pin (see register WAIT_CONT).

The configuration at sequencer step 0 (nRES_MODE) enables the assertion of nRESET at the end

of a power down sequence and starts the reset timer during the consecutive powering up.

This is also true for partial POWERDOWN mode, when the sequencer powers down to pointer

position PART_DOWN.

The reset timer will start to run from the selected event RESET_EVENT and release the nRESET

port after the reset timer has expired (see also description for powering up from NO-POWER/RESET

mode.

DA9021 Datasheet(PDF) 63 Page - Dialog Semiconductor

DA9021 Datasheet(HTML) 63 Page - Dialog Semiconductor

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