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DA9021 Datasheet(PDF) 66 Page - Dialog Semiconductor

Part # DA9021
Description  System PMIC with high efficiency USB power manager
PDF  142 Pages
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Manufacturer  DIALOG [Dialog Semiconductor]
Direct Link  http://www.dialog-semiconductor.com/
Logo DIALOG - Dialog Semiconductor

DA9021 Datasheet(HTML) 66 Page - Dialog Semiconductor

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DA9021/22
System PMIC with high efficiency USB power manager
Datasheet
Revision 2.5
17-Feb-2017
CFR0011-120-00 Rev 5
66 of 142
© 2017 Dialog Semiconductor
Register
address
Bit
Type
Label
Default
Description
6
R
SEQUENCING
0
0: Sequencer is idle
1: Sequencer is processing IDs
7
R
COMP_DET
0
0: Comparator at ADCIN5 (1.2 V) not asserted
1: Comparator asserted
Table 41: STATUS_C
Register
address
BIT
TYPE
LABEL
DEFAUL
T
DESCRIPTION
R3
STATUS_C
0
R
GPI0
0
GPI0 level or ADCIN4 threshold indicator (‘1’
when overriding high limit)
1
R
GPI1
0
GPI1 level or ADCIN5
threshold indicator (‘1’
when overriding high limit)
Table 42: STATUS_D
Register
address
Bit
Type
Label
Default
Description
R4
STATUS_D
0
R
GPI8
0
GPI8/SYS_EN level
1
R
GPI9
0
GPI9/PWR_EN level
2
R
GPI10
0
GPI10/PWR1_EN level
4
R
GPI12
0
GPI12/EXT_WAKEUP/READY level
5
R
GPI13
0
GPI13 level
6
R
GPI14
0
GPI14 level
7
R
GPI15
0
GPI15 level
The EVENT registers hold information about events that have occurred in DA9021/22. Events are
triggered by a change in the status registers that contains the status of monitored signals. When an
EVENT bit is set in the event register the nIRQ signal is asserted (unless the nIRQ is masked by a bit
in the IRQ mask register). The nIRQ is also masked during the power-up sequence and will not be
released until the event registers have been cleared.
The IRQ triggering event register is
cleared from the host by writing a byte containing a ‘1’ at the bit
to be reset (bits written containing a
‘0’ will leave the related event register bits unchanged thus
avoiding accidentally clearing events that occur after the initial event register read). New events that
occur during clearing will be delayed before they are passed to the event register, ensuring that the
host controller does not miss them.
Table 43: EVENT_A
Register
address
Bit
Type
Label
Default
Description
R5
EVENT_A
1
R
E_VBUS_DET
0
VBUS 4.4 V detection caused event
3
R
E_VBUS_REM
0
VBUS removal caused event
4
R
E_VDD_LOW
0
VDDOUT less than VDDOUT_MON threshold
caused event
5
R
E_ALARM
0
RTC alarm caused event
6
R
E_SEQ_RDY
0
Sequencer reached stop position caused
event
7
R
E_COMP_1V2
0
1.2 V comparator caused event



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