DA9021 datasheet(62/142 Pages) DIALOG

62 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

62 of 142

Action

Sequencer time slot

Comment

Assert/Release GP_FB2

GP_RISE1_STEP

Assert/Release GP_FB2

GP_RISE2_STEP

Release/Assert GP_FB2

GP_FALL1_STEP

Release/Assert GP_FB2

GP_FALL2_STEP

Wait for active state at GPI 10

WAIT_STEP

NOTE

IDs (for example supplies) not controlled by the sequencer should point into step 0.

Sequencer ID

(OTP cell)

Time slot

POWER_END

SYSTEM_END

OSC

Programmable

4-bit OTP

Start/Stop

SYS_EN

OTP

Enable

MAX_COUNT

Sequencer

PART_DOWN

SYSTEM

POWER

POWER1

Power Domain

PART_DOWN

Figure 36: Allocation of supplies (IDs) into to the sequencer time slots

To continue the sequencer checks for PWR_EN to be asserted (via PWR_EN port, register write or

OTP). When this is available the feedback signal READY will be asserted and supplies of domain

POWER will be enabled sequentially. The sequencer stops at step POWER_END, releases the

READY signal, asserts PWR_UP, asserts the E_SEQ_RDY interrupt, starts the ACTIVE mode of

DA9021/22 and releases an asserted EXT_WAKEUP signal.

A third power domain POWER1 can be enabled from PWR1_EN (asserted via PWR1_EN port,

asserts PWR1_UP and asserts the E_SEQ_RDY interrupt. The READY signal will be asserted as

long as IDs are processed (if enabled). The domain POWER1 offers no dedicated status indicator,

but the end of its power-up sequence can be selected to start the RESET timer.

The delay between the steps of a sequence is controlled via a 4-bit OTP programmable timer unit

SEQ_TIME with a default delay of 1285 µs per step (minimum 32 µs and max. 816 ms). The delay

time between individual supplies can be extended by leaving consecutive steps having no IDs

pointing to it (dummy supply), which provides an independent delay configured via control

SEQ_DUMMY. The delay timers are configured with their default values from OTP (R43) every time

before powering up inside domain SYSTEM.

NOTE

During entering and leaving a power domain a 32 µs delay will always be inserted.

When DA9021/22 is powering down, the sequencer will disable the supplies in reverse order and

timing. Supplies that are configured with a preset value (LDOx_CONF or BUCKxxx_CONF bit is set)

will not be disabled but configured with their preset voltage when the related time slot/ID is

DA9021 Datasheet(PDF) 62 Page - Dialog Semiconductor

DA9021 Datasheet(HTML) 62 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL