DA9021 datasheet(54/142 Pages) DIALOG

54 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

54 of 142

SLAVEadr

REGadr

DATA

S = START condition

A = Acknowledge (low)

P = STOP condition

W = Write (low)

Master to Slave

Slave to Master

7-bits

1-bit

8-bits

Figure 30: 2-wire byte write (SO/DATA line)

When the host reads data from a register it first has to write access DA9021/22 with the target

START condition. After receiving the data the host sends Not Acknowledge and terminates the

transmission with a STOP condition:

SLAVEadr W

REGadr

SLAVEadr

S = START condition

A = Acknowledge (low)

Sr = Repeated START condition

* = Not acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

SLAVEadr

7-bits

DATA

1-bit

8-bits

Slave to Master

SLAVEadr W

REGadr

7-bits

1-bit

8-bits

Figure 31: Examples of 2-wire byte read (SO/DATA line)

NOTE

The slave address after the Repeated START condition must be the same as the previous slave address.

Consecutive (page) write mode is supported if the master sends several data bytes following a slave

address, stores the received data and sends an Acknowledge until the master sends the STOP

condition.

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = Not Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

DATA

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 32: 2-wire page write (SO/DATA line)

An alternate write mode receiving alternated register address and data can be configured to support

host repeated write operations that access several but non-consecutive registers.

Data will be stored at the previously received register address:

SLAVEadr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = Not Acknowledge

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

REGadr

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 33: 2-wire repeated write (SO/DATA line)

If a new START or STOP condition occurs within a message, the bus will return to IDLE mode.

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