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DA9021 Datasheet(PDF) 24 Page - Dialog Semiconductor |
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DA9021 Datasheet(HTML) 24 Page - Dialog Semiconductor |
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24 / 142 page ![]() DA9021/22 System PMIC with high efficiency USB power manager Datasheet Revision 2.5 17-Feb-2017 CFR0011-120-00 Rev 5 24 of 142 © 2017 Dialog Semiconductor 8.4 4-wire control bus 1 2 4 5 8 9 11 3 A6 A5 A4 BIT 7 R/W BIT 1 LSB LSB BIT 1 Address R/W DATA SO SI SK nCS 7 6 Figure 5: 4-wire control bus timing diagram NOTE The above timing is valid for active low and high CS Table 11: 4-wire timing Parameter Symbol Label in Figure 5 Min Typ Max Unit Cycle time tC 1 70 ns Enable lead time tCSS 2, from CS active to first SK edge 20 ns Enable lag time tSCS 3, from last SK edge to CS idle 20 ns Clock low time tCL 4 0.4 * tC ns Clock high time tCH 5 0.4 * tC ns Data in setup time tSIS 6 5 ns Data in hold time tSIH 7 5 ns Data out valid time tSOV 8 22 ns Data out hold time tSOH 9 6 ns Data access time tH 10 22 ns 8.5 Oscillator characteristics Table 12: Oscillator Parameter Symbol Condition Min Typ Max Unit Internal oscillator frequency before trimming 1.4 2.0 2.6 MHz after trimming 1.9 2.1 |
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