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DA9021 Datasheet(PDF) 56 Page - Dialog Semiconductor |
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DA9021 Datasheet(HTML) 56 Page - Dialog Semiconductor |
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56 / 142 page ![]() DA9021/22 System PMIC with high efficiency USB power manager Datasheet Revision 2.5 17-Feb-2017 CFR0011-120-00 Rev 5 56 of 142 © 2017 Dialog Semiconductor 13 DA9021 operating modes 13.1 ACTIVE mode A running application is typically in ACTIVE mode. In addition to PMIC core functions (for example LDOCORE, Binary Coded Decimal (BCD) counter and internal oscillator) in ACTIVE mode a set of supplies and peripheral features like the battery charger and GP-ADC are usually enabled. If required in ACTIVE mode the host processor can take over the control of the automatic battery charging block and is able to respond to any faults that have been detected. Status information can be read from the host processor via the power manager bus and DA9021/22 can flag interrupt requests to the host via a dedicated interrupt port (nIRQ). Temperature and voltages inside and outside the DA9021/22 can be monitored and any fault conditions are flagged to the host processor. 13.2 POWERDOWN mode DA9021/22 is in POWERDOWN mode whenever the power domain SYSTEM is disabled (even partially). This can be achieved when progressing from RESET mode or by returning from ACTIVE mode. A return from ACTIVE mode is initiated by low power mode instructions from the host or occurs as an interim state during an application shutdown to RESET mode. During POWERDOWN mode the LDOCORE, the bandgap, the nONKEY and the BCD counter are active. Dedicated power supplies can be enabled during POWERDOWN mode if power down voltages have been pre-configured during ACTIVE mode. In addition GPIO-ports, the GP-ADC, battery charger and the control interfaces remain enabled if not disabled via register PD_DIS. Disabling blocks during POWERDOWN mode will save quiescent current especially if all blocks are disabled that require an oscillator clock. If the host will no longer communicate during POWERDOWN mode the control interfaces may be temporarily disabled (see controls PM- IF_PD/HS-2-wire_PD.). Dedicated power supplies can be enabled in POWER-DOWN mode if power down voltages has been pre-configured during ACTIVE mode. The internal oscillator (2 MHz) will only run on demand (for example for a running GP-ADC or enabled bucks that are not forced to PFM mode). The digital control logic of disabled features (regulators, bucks, chargers, GP-ADC, and others) will be disconnected from the clock tree by clock gating, so that the device offers an optimised dissipation power in POWERDOWN mode. Following the next wakeup event all supplies are re-configured with their default voltage values from OTP and the sequencer timers are set to their default OTP values. If the POWERDOWN mode was caused by releasing SYS_EN the sequencer pointer is located at position 0 allowing default enabling / disabling of supplies (beside LDOCORE). 13.3 RESET mode DA9021/22 is in RESET mode whenever a complete application reset is required. The RESET mode happens after cold start when progressing from NO-POWER mode or can be forced by the user via a pressed reset switch that is connected to port nSHUTDOWN, a long press of nONKEY (if the RESET feature was enabled) or a long parallel assertion of GPIO14 and GPIO15 (if this RESET feature was enabled), from the host processor by asserting port nSHUTDOWN or via an error detection from DA9021/22. DA9021/22 error conditions that force a RESET mode: ● An under-voltage detected at VDDOUT (VDDOUT < VDD_FAULT_LOWER) ● An internal die over-temperature detected ● An over voltage or over current at the boost In order to allow the host to determine the reason for the RESET a FAULTLOG register records the cause. When returning from POWERDOWN mode the RESET mode will be achieved after powering down domain SYSTEM completely and continue towards a state with absolute minimum current consumption, with the only active circuits being LDOCORE, the BCD counter, the band gap and the |
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