DA9021 datasheet(5/142 Pages) DIALOG

5 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

5 of 142

24.3 LDOs and switched mode supplies................................................................................... 137

24.4 Crystal oscillator ................................................................................................................ 137

24.5 DA9021 thermal connection, land pad and stencil design ................................................ 138

25 Definitions .................................................................................................................................. 139

25.1 Power dissipation and thermal design .............................................................................. 139

25.2 Regulator parameters ....................................................................................................... 139

25.2.1

Dropout voltage ................................................................................................. 139

25.2.2

Power supply rejection....................................................................................... 140

25.2.3

Line regulation ................................................................................................... 140

25.2.4

Load regulation .................................................................................................. 140

26 Ordering information ................................................................................................................ 141

26.1 Additional applications information ................................................................................... 141

Revision history............................................................................................................................... 141

Figures

Figure 1: Block diagram....................................................................................................................... 10

Figure 2: PCB board DA9021 pad arrangement (view from the top) .................................................. 12

Figure 3: PCB board DA9022 pad arrangement (view from the top) .................................................. 13

Figure 4: Pad arrangement colour key ................................................................................................ 14

Figure 5: 4-wire control bus timing diagram ........................................................................................ 24

Figure 6: Schematics of the RTC oscillator and counter functionality................................................. 42

Figure 7: BUCKPERI efficiency curves ............................................................................................... 43

Figure 8: BUCKCORE efficiency curves ............................................................................................. 43

Figure 9: BUCKPRO efficiency curves ................................................................................................ 43

Figure 10: BUCKMEM efficiency curves ............................................................................................. 43

Figure 11: Typical buck line transient .................................................................................................. 43

Figure 12: Typical buck load transient................................................................................................. 43

Figure 13: Typical LDO load regulation ............................................................................................... 44

Figure 14: Typical LDO drop-out voltage ............................................................................................ 44

Figure 15: Typical LDO line transient .................................................................................................. 44

Figure 16: LDO load transient ............................................................................................................. 44

Figure 17: Typical LDO voltage vs temperature.................................................................................. 44

Figure 18: ADC DNL performance ...................................................................................................... 45

Figure 19: ADC INL performance ........................................................................................................ 45

Figure 20 Power path behaviour USB100 mode................................................................................. 45

Figure 21 Power path behaviour USB500 mode................................................................................. 45

Figure 22: Transitioning supply from USB 5 V (via VBUS) to VBAT................................................... 45

Figure 23: Control ports and interface ................................................................................................. 46

Figure 24: Schematic of 4-wire and 2-wire power manager bus......................................................... 49

Figure 25: 4-

wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’) .................... 50

Figure 26: 4-

wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘1’) .................... 51

Figure 27: 4-

wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘0’) .................... 51

Figure 28: 4-

wire host write and read timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’) .................... 52

Figure 29: Timing of 2-wire START and STOP condition ................................................................... 53

Figure 30: 2-wire byte write (SO/DATA line) ....................................................................................... 54

Figure 31: Examples of 2-wire byte read (SO/DATA line)................................................................... 54

Figure 32: 2-wire page write (SO/DATA line) ...................................................................................... 54

Figure 33: 2-wire repeated write (SO/DATA line)................................................................................ 54

Figure 34: Start-up from NO-POWER to POWERDOWN mode......................................................... 59

Figure 35: Content of OTP power sequencer register cell .................................................................. 61

Figure 36: Allocation of supplies (IDs) into to the sequencer time slots ............................................. 62

Figure 37: Typical power-up timing ..................................................................................................... 81

Figure 38: Power mode transitions...................................................................................................... 82

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