DA9021 datasheet(61/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

61 of 142

All buck converters and five LDOs of DA9021/22 have received a unique sequencer ID. The power-

up sequence is then defined by an OTP register bank that contains a series of supplies (and other

features) which are pointing towards a sequencer time slot. Several supplies can point in to the same

time slot and by that will be enabled by the sequencer in parallel. Time slots that have no IDs

pointing towards it are dummy steps that insert a configurable time delay (marked

as ‘D’ in Figure

36). Supplies that are not pointing towards a sequencer time slot (with a step number greater than

zero and less than MAX_COUNT) will not be enabled by the power sequencer and have to be

controlled individually by the host (via the power manager bus).

OTP Step 0

LSB

If asserted all supplies are set to default mode

when processing step 0 (beside LDOCORE)

OTP Step 1 - 15

4-bit

0: Dummy (do nothing)

– 15: Enable supply described by ID

0: No assertion of nRESET during POWER-DOWN mode

1: Start reset timer from selected event during powering up

Not used

MSB

Configure sequencer

Figure 35: Content of OTP power sequencer register cell

During power-up the sequencer will start at step 0 where the sequencer behaviour is configured. If

DEF_SUPPLY is asserted this includes an optional enabling of supplies (depending on the OTP

default settings of the supplies). If SYS_EN was asserted via port (or OTP) the sequencer will assert

the READY signal (if selected for the feedback pin) and continue with step 1 which enables all

supplies (features) from the OTP register bank that are pointing towards step 1. The sequencer will

progress until it has reached the position of pointer SYSTEM_END. Now all supplies of the first

power domain SYSTEM are enabled and DA9021/22 will release the READY signal and assert the

E_SEQ_RDY interrupt.

NOTE

It is recommended that supplies having an asserted ENABLE bit in the OTP are not controlled via IDs of the

power sequencer if DEF_SUPPLY is asserted (IDs of these supplies should point into time slot 0).

Table 37: Power sequencer controlled actions

Action

Sequencer time slot

Comment

Step 0: Configure power sequencer

ID_0

LDO1_EN

LDO1_STEP

LDO3_EN

LDO3_STEP

LDO7_EN

LDO7_STEP

LDO9_EN

LDO9_STEP

LDO10_EN

LDO10_STEP

PD_DIS

PD_DIS_STEP

BCORE_EN

BUCKCORE_STEP

BPRO_EN

BUCKPRO_STEP

DA9021 only

BMEM_EN

BUCKMEM_STEP

BPERI_EN

BUCKPERI_STEP

DA9021 only

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