DA9021 datasheet(86/142 Pages) DIALOG

86 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

86 of 142

17 Voltage regulators

Three types of low dropout regulators are integrated on the DA9021/22, each optimised for

performance depending on the most critical parameter of the circuitry supplied. For high performance

analogue supplies (for example audio) the regulators have been designed to offer high PSRR and

low noise, for the digital supplies PSRR is relaxed saving quiescent current and for the PMIC

core/RTC supplies quiescent current has been optimised as the most important performance

parameters. The regulators employ Dialog Semiconductor’s Smart Mirror™ dynamic biasing,

removing the need for a low power operating mode and associated software or hardware overhead.

Smart Mirror™ technology guarantees a high phase margin within the regulator control loop and has

been designed to offer stable performance with small output capacitances over a wide range of

output currents. The circuit technique offers significantly higher gain bandwidth performance than

conventional designs, enabling higher power supply rejection performance at higher frequencies.

PSRR is also maintained across the full operating current range however quiescent current

consumption is scaled to demand giving improved efficiency when current demand is low.

Figure 39: Smart Mirror

™ voltage regulator

The regulator output voltages are fully programmable via the control interface allowing optimisation of

the complete system for maximum performance and power efficiency. For security reasons the re-

programming of output voltages from the control interfaces can be disabled. The default output

voltage is loaded from after start-up from OTP.

A power saving mode is not required for the LDOs due to the use of dynamic biasing in the LDO

internal circuitry, so when operating at low current, the quiescent current taken by the regulator is

automatically minimised. LDO1 to LDO10 can optionally be supplied from a buck output (VDD <

2.8 V), in this mode some specification parameters will change.

LDO1 to LDO10 can be controlled inside the power manager sequence. If enabled at sequencer step

0 (bit DEF_SUPPLY) supplies can be default enabled via OTP whenever the sequencer passes step

0 (OTP settings are used). To limit the battery rush current it is recommended that no more than one

supply (including bucks) is enabled at step 0

When powering down (for example to POWERDOWN mode) sequencer controlled supplies can be

pre-configured with a new target voltage (LDOx_CONF bit is set). If LDOx_CONF was asserted in

DA9021 Datasheet(PDF) 86 Page - Dialog Semiconductor