DA9021 datasheet(58/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

58 of 142

● a write to register R106 will end the first programming sequence

● a write to register R61 will end the second programming sequence

During these programming sequences any registers can be written to in any order The sequence will

terminate after the appropriate release register has been written to.

NOTE

To correctly configure DA9021/22 registers, R10 to R105 should be programmed during the first sequence and

FAULT LOG register (R9) bit VDD_FAULT has to be cleared

by writing a ‘1’. Registers R14 and R43 to R61

should be programmed during the second sequence.

The host can determine whether DA9021/22 is in the first or second programming sequence by

reading the FAULT LOG register. If a read of the FAULT LOG register bit VDD_FAULT returns a

zero, then the DA9021/22 is in the second programming sequence otherwise it is in the first.

After the first programming sequence has been completed DA9021/22 will be in POWERDOWN

mode. Progression from this mode is determined by the values programmed for SYS_EN and

AUTO_BOOT.

If DA9021/22 has been directed to progress from POWERDOWN mode then it will drive pin

nVDD_FAULT low for a second time to request that the software performs the second programming

sequence.

Once the second programming sequence has completed, the progress of the power-up sequence will

be controlled by the values loaded during the programming sequence.

The programmed configuration can be identified by reading the fuse register CONFIG_ID.

NOTE

During POWER COMMANDER mode the fault detection status bit VDD_FAULT and the level at the related pin

nVDD-FAULT do not match and do not indicate a low voltage level at VDDOUT. An enabled shutdown from the

5 s assertion of GPIO14/15 will be ignored during POWER COMMANDER mode.

13.6 Start up from NO POWER mode

13.6.1

Power-On-Reset (nPOR)

To guarantee the correct start-up of DA9021/22 an internal power-on-reset nPOR (active low) is

generated for the initial connection of either a supply or a good battery following a phase of not being

supplied with sufficient power. To allow DA9021/22 to start up even if the main battery is completely

discharged an internal VDDREF rail is used to supply the charger blocks, comparators and the

control logic. If no charger is present VDD_REF is switched to the main battery

While VDDCORE < VPOR_UPPER the internal nPOR is asserted and DA9021/22 will not switch on

(NO-POWER mode). When VDDCORE rises above VPOR_UPPER the nPOR is negated,

LDOCORE will be switched on, the BCD counter and FAULT_LOG register is reset and DA9021/22

progresses to RESET mode.

When an external charger is detected (rising edge on VBUS_DET) having no or only a deep

discharged main battery connected to DA9021/22 the internal charger, oscillator and bandgap are

enabled and the whole OTP trim block is read and stored to the register bank. If the supply voltage is

below the charger detection threshold (VCH_THR) after a debouncing period of tdelay (10 ms to

allow for de-bouncing of the input signal and the bandgap reference to settle) the device returns to

RESET mode.

If the external charger is still present and the CHG_ATT comparator flags a minimum of 100 mV

head room from charger input VCENTER to VDDOUT, DA9021/22 starts up the charger buck to

supply VDDOUT at the default current limit (loaded from OTP) and starts supplying power to

VDDOUT, which enables an application start-up also with a flat battery. When VDDOUT rises above

VDDOUT_MIN DA9021/22 enters the POWERDOWN mode. If this does not happen within 128 ms it

will return to RESET mode.

DA9021 Datasheet(PDF) 58 Page - Dialog Semiconductor

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