DA9021 datasheet(52/142 Pages) DIALOG

52 / 142 page

DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

52 of 142

R/Wn

nCS

4-WIRE WRITE

R/Wn

nCS

4-WIRE READ

latch data

HI-Z

Figure 28: 4-wire host write and r

ead timing (nCS_POL = ‘0’, CPOL = ‘1’, CPHA = ‘1’)

Table 35: 4-wire interface summary

PARAMETER

Signal lines

nCS

Chip select

SI Serial input data

Master out Slave in

SO Serial output data

Master in Slave out

Transmission clock

Interface

Push-pull with tristate

Supply voltage

VDD_IO

1.6 V to 3.3 V

Data rate

Effective read/write data

Up to 7 Mbps

Transmission

Half-duplex

MSB first

16-bit cycles

7-bit address, 1-bit read/write, 8-bit

data

Configuration

CPOL

Clock polarity

CPHA

Clock phase

NCS is active low/high

NOTE

Reading the same register at high clock rates directly after writing it does not guarantee a correct value. It is

recommended to keep a delay of one frame until re-accessing a register that has just been written (for example

by writing/reading another register address in between).

DA9021 Datasheet(PDF) 52 Page - Dialog Semiconductor

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