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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

57 of 142

VDD_REF, VBUS, ACC_ID_DET and VDDOUT comparators. Except LDO1, if correctly configured,

other supplies and blocks on DA9021/22 are automatically disabled to avoid draining the battery.

During DA9021/22 RESET mode the host processor can be held in a RESET state via port nRESET

which is always asserted to low when DA9021/22 progresses from RESET mode (for example after

cold start from NO-POWER mode) and can be asserted (depending on configuration of sequencer

step 0) when the sequencer has finished powering down domain SYSTEM (even partially).

Except E_B_FAULT and E_ALARM, all asserted events will automatically be cleared and the

DA9021/22 register configuration will be re-loaded from OTP when leaving RESET mode (with the

exception of AUTO_BOOT in case of emergency charging).

NOTE

FAULT_LOG and other non OTP loaded registers, for example the RTC calendar and alarm, will not be changed

when leaving RESET mode.

Some RESET conditions such as the SHUTDOWN via register bit, will automatically expire over-

temperature. Other conditions like asserting the port nSHUTDOWN need to be released to enable a

progress from RESET to POWERDOWN mode. If the RESET was initiated by a hardware reset from

user keys or port nSHUTDOWN a 500 ms time out will be inserted before trying to power up again.

When the RESET condition has disappeared DA9021/22 requires either a connected good main

battery (VDDOUT > VDD_FAULT_UPPER) or a detected supply (VBUS > VCH_THR) that is able to

provide enough power to VDDOUT (VDDOUT > VDDOUT_MIN) to start-up to POWERDOWN mode.

13.4 NO-POWER mode

DA9021/22 will enter the NO-POWER mode when VDDCORE drops below VPOR_LOWER (for

example during continued discharge of main battery). As long as VDDCORE is now lower than

VPOR_UPPER the core supply LDOCORE, the 32 kHz oscillator and the BCD counter are switched

off, an internal power-on-reset (nPOR) is asserted and only the VDDCORE comparator is active and

checks for a condition that allows DA9021/22 to turn on again. When DA9021/22 detects either a

good main battery or a connected supply charger which rises VDDCORE > VPOR_UPPER it will

reset the BCD counter and FAULT_LOG register and progress to RESET mode.

13.5 POWER COMMANDER mode

This is a special mode for evaluation and configuration. In POWER COMMANDER mode DA9021/22

is configured to load the control register default values from the HS 2-wire interface instead of from

the OTP cells so that un-programmed DA9021 samples will power up and allow a PC running the

Power Commander software to load all the configuration registers. POWER COMMANDER mode is

enabled by connecting TP to VDDCORE.

In RESET-mode DA9021/22 will do an initial OTP read to setup the trim values. However, if the OTP

values loaded into these registers are not as required they can be updated during the subsequent

POWER COMMANDER mode programming sequences.

NOTE

In POWER COMMANDER mode GPI14/15 will be configured for HS-2-wire interface operation (with VDDCORE

as the supply) and GPO13 will be configured as an output for nVDD_FAULT. Any register writes or OTP loads

which can change this configuration are ignored until DA9021/22 has exited from POWER COMMANDER mode.

After the initial OTP read has completed, DA9021/22 informs the system that it is waiting for a

programming sequence by driving nVDD_FAULT low. The software running on the PC monitors

nVDD_FAULT and responds by downloading the values into the configuration registers within

DA9021/22. nVDD_FAULT is automatically released after the release register is loaded.

There are two programming sequences performed in POWER COMMANDER mode. The first takes

place between RESET and POWERDOWN mode and the second takes place between

POWERDOWN and SYSTEM mode. Two release registers are used support these two programming

sequences:

DA9021 Datasheet(PDF) 57 Page - Dialog Semiconductor

DA9021 Datasheet(HTML) 57 Page - Dialog Semiconductor

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