DA9021 datasheet(55/142 Pages) DIALOG

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DA9021/22

System PMIC with high efficiency USB power manager

Datasheet

Revision 2.5

17-Feb-2017

CFR0011-120-00 Rev 5

55 of 142

12.3.2

Alternative high speed 2-wire interface

The high speed 2-wire (HS-2-wire) interface is the alternative serial control bus, which consists of a

DATA (data line) and a CLK (clock line) that can be used as an independent control interface for data

transactions between DA9021/22 and a second host processor. The DA9021/22 HS-2-wire interface

has a configurable 8-bit SLAVE write address (default: 0x92) and a configurable SLAVE read

address (default: 0x93).

The interface is enabled if DATA was selected via configuration GPIO14_PIN. The bus lines have to

be pulled HIGH by external pull-up resistors (2 k

Ω to 20 kΩ range). GPIO15_TYPE defines the

supply rail of the interface (used for input logic levels and the internal pull-up resistors). The controls

GPIO15_PIN and GPIO15_ MODE are disabled when the interface was enabled via GPIO14_PIN.

Whenever the interface receives a READ or WRITE command that includes a matching slave

address it is able to trigger the assertion of an nIRQ including an optional wakeup event (enabled via

GPIO14_ MODE).

NOTE

If the nIRQ assertion from interface access is enabled it may by masked as long as the HS-2-wire is in use (this

nIRQ cannot be cleared via the HS-2_wire interface because every interface access will trigger a re-assertion).

With the exception of the interface base address and the optional wakeup, the characteristics of the

HS-2-wire interface are identical to the power manager 2-wire interface (see above).

NOTE

By connecting TP to VDDCORE the DA9021/22 (POWER COMMANDER mode) will load the register default

values via the HS 2-wire interface instead of from OTP cells. In this mode the interface will be supplied from

VDDCORE (independent to the settings at GPIO15_TYPE).

DA9021 Datasheet(PDF) 55 Page - Dialog Semiconductor