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AD9174 Datasheet(PDF) 114 Page - Analog Devices |
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AD9174 Datasheet(HTML) 114 Page - Analog Devices |
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114 / 164 page  AD9174 Data Sheet Rev. A | Page 114 of 164 Addr. Name Bits Bit Name Settings Description Reset Access 0x1E2 DDSM_CAL_FTW0 [7:0] DDSM_CAL_ FTW[7:0] FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x1E3 DDSM_CAL_FTW1 [7:0] DDSM_CAL_ FTW[15:8] FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x1E4 DDSM_CAL_FTW2 [7:0] DDSM_CAL_ FTW[23:16] FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x1E5 DDSM_CAL_FTW3 [7:0] DDSM_CAL_ FTW[31:24] FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x1E6 DDSM_CAL_MODE_ DEF [7:3] RESERVED Reserved. 0x0 R 2 DDSM_EN_CAL_ ACC Enable clock calibration accumulator. This bit must be first set high, and then must load the calibration FTW into Register 0x1E2 to Register 0x1E5 to take effect. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0 Disabled (does not clock the calibration frequency accumulator). 1 Enables (turns on the clock to the calibration frequency accumulator). 1 DDSM_EN_CAL_ DC_INPUT Enable dc input to calibration DDS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0 Mux in datapath signal to the input of the final DDS. 1 Mux in dc to the input of the final DDS. 0 DDSM_EN_CAL_ FREQ_TUNE Enable tuning of the signal to calibration frequency for DAC0 only. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0 Disable calibration frequency tuning. 1 Enable calibration frequency tuning. 0x1E7 DATAPATH_NCO_ SYNC_CFG [7:2] RESERVED Reserved. 0x0 R 1 ALL_NCO_SYNC_ ACK Acknowledge signal that all the active NCOs are loaded. This bit is the acknowledge indicator for both the START_NCO_SYNC bit (Bit 0 of this register) and the NCORST_ AFTER_ROT_EN bit (Register 0x03B, Bit 4) method of resetting the NCOs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R 0 START_NCO_SYNC Used to start the sync of the NCOs on a rising edge of the SPI bit or SYSREF± signal, depending on which is chosen as the update trigger. Upon receiving a trigger, the FTWs are loaded first, and then a synchronization occurs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. 0x0 R/W 0x200 MASTER_PD [7:1] RESERVED Reserved. 0x0 R 0 SERDES_MASTER_ PD Powers down the entire JESD204B receiver analog (all eight channels and bias). 0x1 R/W |
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