AD9174 datasheet(115/164 Pages) AD

115 / 164 page

Data Sheet

AD9174

Rev. A | Page 115 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x201

PHY_PD

[7:0]

PHY_PD

SPI override to power down the individual

PHYs. Bit 0 controls the SERDIN0± PHY.

0xEE

R/W

Bit 1 controls the SERDIN1± PHY.

Bit 2 controls the SERDIN2± PHY.

Bit 3 controls the SERDIN3± PHY.

Bit 4 controls the SERDIN4± PHY.

Bit 5 controls the SERDIN5± PHY.

Bit 6 controls the SERDIN6± PHY.

Bit 7 controls the SERDIN7± PHY.

0x203

GENERIC_PD

[7:2]

RESERVED

Reserved.

0x0

PD_

SYNCOUT0E

Powers down the

SYNCOUT0±E

driver.

0x0

R/W

Enables the

SYNCOUT0±E

output pins.

Powers down the

SYNCOUT0±E

output pins.

PD_

SYNCOUT1E

Powers down the

SYNCOUT1±E

driver.

0x1

R/W

Enables the

SYNCOUT1±E

output pins.

Powers down the

SYNCOUT1±E

output pins.

0x206

CDR_RESET

[7:1]

RESERVED

Reserved.

0x0

CDR_PHY_RESET

PHY reset control bit. Set this bit to 1 to

take the PHYs out of reset during device

operation.

0x0

R/W

0x210

CBUS_ADDR

[7:0]

SERDES_CBUS_

ADDR

SERDES configuration control register to

set SERDES configuration address controls.

0x0

R/W

0x212

CBUS_WRSTROBE_

PHY

[7:0]

SERDES_CBUS_

WR0

SERDES configuration control register to

commit the SERDES configuration controls

written.

0x0

R/W

0x213

CBUS_WRSTROBE_

OTHER

[7:1]

RESERVED

Reserved.

0x0

SERDES_CBUS_

WR1

SERDES configuration control register to

commit the SERDES configuration controls

written.

0x0

R/W

0x216

CBUS_WDATA

[7:0]

SERDES_CBUS_

DATA

SERDES configuration control register to

set the SERDES configuration control data.

0x0

R/W

0x240

EQ_BOOST_PHY_

3_0

[7:6]

EQ_BOOST_PHY3

Equalizer setting for PHY 3 based on

insertion loss of the system.

0x3

R/W

Insertion loss ≤ 11 dB.

Insertion loss > 11 dB.

[5:4]

EQ_BOOST_PHY2

Equalizer setting for PHY 2 based on

insertion loss of the system.

0x3

R/W

Insertion loss ≤ 11 dB.

Insertion loss > 11 dB.

[3:2]

EQ_BOOST_PHY1

Equalizer setting for PHY 1 based on

insertion loss of the system.

0x3

R/W

Insertion loss ≤ 11 dB.

Insertion loss > 11 dB.

[1:0]

EQ_BOOST_PHY0

Equalizer setting for PHY 0 based on

insertion loss of the system.

0x3

R/W

Insertion loss ≤ 11 dB.

Insertion loss > 11 dB.

0x234

CDR_BITINVERSE

[7:0]

SEL_IF_

PARDATAINV_DES_

RC_CH

Output data inversion bit controls. Set Bit x

corresponding to PHY x to invert the bit

polarity.

0x66

R/W

Not inverted.

Inverted.

AD9174 Datasheet(PDF) 115 Page - Analog Devices

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