Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

AD9174 Datasheet(PDF) 118 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 118 Page - Analog Devices

Back Button AD9174 Datasheet HTML 114Page - Analog Devices AD9174 Datasheet HTML 115Page - Analog Devices AD9174 Datasheet HTML 116Page - Analog Devices AD9174 Datasheet HTML 117Page - Analog Devices AD9174 Datasheet HTML 118Page - Analog Devices AD9174 Datasheet HTML 119Page - Analog Devices AD9174 Datasheet HTML 120Page - Analog Devices AD9174 Datasheet HTML 121Page - Analog Devices AD9174 Datasheet HTML 122Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 118 / 164 page
background image
AD9174
Data Sheet
Rev. A | Page 118 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x280
PLL_ENABLE_CTRL
[7:3]
RESERVED
Reserved.
0x0
R
2
LOLSTICKYCLEAR_
LCPLL_RC
Clears out loss of lock bit.
0x0
R/W
1
LDSYNTH_LCPLL_
RC
Pulse high to start VCO calibration
(without restarting the regulator or
remeasuring the temperature).
0x0
R/W
0
SERDES_PLL_
STARTUP
SERDES circuitry blocks are powered off
when this bit is set to 0. Set this bit to 1 at
the end of the SERDES configuration writes.
When this bit is set to 1, it powers up the
SERDES PLL blocks and starts the LDO and
calibration routine to lock the PLL auto-
matically to the appropriate lane rate based
on the JESD204B mode and interpolation
options programmed in the device. The
SERDES_PLL_LOCK bit (Register 0x281,
Bit 0) reads 1 when the PLL achieves lock.
0x1
R/W
0x281
PLL_STATUS
[7:1]
RESERVED
Reserved.
0x0
R
0
SERDES_PLL_LOCK
PLL is locked when this bit is high.
0x0
R
0x300
GENERAL_JRX_
CTRL_0
[7:4]
RESERVED
Reserved.
0x0
R
3
LINK_MODE
Reads back 0 when in single-link mode
and 1 when in dual-link mode.
0x0
R/W
2
LINK_PAGE
Link paging. This bit selects which link
register map is used. This paging affects
Register 0x400 to Register 0x4BB.
0x0
R/W
0
Page QBD0 for Link 0.
1
Page QBD1 for Link 1.
[1:0]
LINK_EN
These bits bring up the JESD204B digital
receiver when all link parameters are
programmed and all clocks are ready. Bit 0
applies to Link 0, whereas Bit 1 applies to
Link 1. Link 1 is only available in dual-link
mode.
0x0
R/W
0x302
DYN_LINK_
LATENCY_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DYN_LINK_
LATENCY_0
Dynamic link latency, Link 0. Latency
between the LMFC receiver for Link 0 and
the last arriving LMFC boundary in units of
PCLK cycles.
0x0
R
0x303
DYN_LINK_
LATENCY_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
DYN_LINK_
LATENCY_1
Dynamic link latency, Link 1. Latency
between the LMFC receiver for Link 1 and
the last arriving LMFC boundary in units of
PCLK cycles.
0x0
R
0x304
LMFC_DELAY_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_DELAY_0
LMFC delay, Link 0. Delay from the LMFC
to the LMFC receiver for Link 0 in units of
PCLK cycles.
0x0
R/W
0x305
LMFC_DELAY_1
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_DELAY_1
LMFC delay, Link 1. Delay from the LMFC
to the LMFC receiver for Link 1 in units of
PCLK cycles.
0x0
R/W
0x306
LMFC_VAR_0
[7:6]
RESERVED
Reserved.
0x0
R
[5:0]
LMFC_VAR_0
Variable delay buffer, Link 0. These bits set
when data is read from a buffer to be con-
sistent across links and power cycles (in units
of PCLK cycles). The maximum value is
0xC.
0x3F
R/W



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com