AD9174 datasheet(120/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 120 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x30A

XBAR_LN_4_5

[7:6]

RESERVED

Reserved.

0x0

[5:3]

LOGICAL_LANE5_

SRC

Logical Lane 5 source. These bits select a

physical lane to be mapped onto Logical

Lane 5.

0x5

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

[2:0]

LOGICAL_LANE4_

SRC

Logical Lane 4 source. These bits select a

physical lane to be mapped onto Logical

Lane 4.

0x4

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

0x30B

XBAR_LN_6_7

[7:6]

RESERVED

Reserved.

0x0

[5:3]

LOGICAL_LANE7_

SRC

Logical Lane 7 source. These bits select a

physical lane to be mapped onto Logical

Lane 7.

0x7

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

[2:0]

LOGICAL_LANE6_

SRC

Logical Lane 6 source. These bits select a

physical lane to be mapped onto Logical

Lane 6.

0x6

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

0x30C

FIFO_STATUS_REG_0

[7:0]

LANE_FIFO_FULL

Bit x corresponds to FIFO full flag for data

from SERDINx±.

0x0

0x30D

FIFO_STATUS_REG_1

[7:0]

LANE_FIFO_EMPTY

Bit x corresponds to FIFO empty flag for

data from SERDINx±.

0x0

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