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AD9174 Datasheet(PDF) 121 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 121 Page - Analog Devices

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Data Sheet
AD9174
Rev. A | Page 121 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x311
A
SYNCOUTE
A
_GEN_0
[7:4]
RESERVED
Reserved.
0x0
R
3
EOMF_MASK_1
Mask end of multiframe (EOMF) from
QBD1. Assert
A
SYNCOUT1±E
A
based on the
loss of the multiframe synchronization.
0x0
R/W
0
Do not assert
A
SYNCOUT1±E
A
on loss of
multiframe.
1
Assert
A
SYNCOUT1±E
A
on loss of multiframe.
2
EOMF_MASK_0
Mask EOMF from QBD0. Assert
A
SYNCOUT0±E
A
based on the loss of the
multiframe synchronization.
0x0
R/W
0
Do not assert
A
SYNCOUT0±E
A
on loss of
multiframe.
1
Assert
A
SYNCOUT0±E
A
on loss of multiframe.
1
EOF_MASK_1
Mask EOF from QBD1. Assert
A
SYNCOUT1±E
A
based on loss of frame synchronization.
0x0
R/W
0
Do not assert
A
SYNCOUT1±E
A
on loss of
frame.
1
Assert
A
SYNCOUT1±E
A
on loss of frame.
0
EOF_MASK_0
Mask EOF from QBD0. Assert
A
SYNCOUT0±E
A
based on loss of frame synchronization.
0x0
R/W
0
Do not assert
A
SYNCOUT0±E
A
on loss of
frame.
1
Assert
A
SYNCOUT0±E
A
on loss of frame.
0x312
A
SYNCOUTE
A
_GEN_1
[7:4]
A
SYNCE
A
_ERR_DUR
Duration of
A
SYNCOUTx±E
A
low for the
purposes of the synchronization error
report. Duration = (0.5 + code) PCLK
cycles. To most closely match the specified
value, set these bits as close as possible to
f/2 PCLK cycles. These bits are shared
between
A
SYNCOUT0±E
A
and
A
SYNCOUT1±E
A
.
0x0
R/W
[3:0]
RESERVED
Reserved.
0x0
R/W
0x315
PHY_PRBS_TEST_EN
[7:0]
PHY_TEST_EN
Enable PHY BER by ungating the clocks.
0x0
R/W
0
PHY test disable.
1
PHY test enable.
0x316
PHY_PRBS_TEST_
CTRL
7
RESERVED
Reserved.
0x0
R
[6:4]
PHY_SRC_ERR_CNT
0x0
R/W
000
Report Lane 0 error count.
001
Report Lane 1 error count.
010
Report Lane 2 error count.
011
Report Lane 3 error count.
100
Report Lane 4 error count.
101
Report Lane 5 error count.
110
Report Lane 6 error count.
111
Report Lane 7 error count.
[3:2]
PHY_PRBS_PAT_SEL
Select PRBS pattern for PHY BER test.
0x0
R/W
00
PRBS7.
01
PRBS15.
10
PRBS31.
11
Not used.
1
PHY_TEST_START
Starts and stops the PHY PRBS test.
0x0
R/W
0
Test not started.
1
Test started.



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