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AD9174 Datasheet(PDF) 125 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 125 Page - Analog Devices

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Data Sheet
AD9174
Rev. A | Page 125 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x404
F_REG
[7:0]
F_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
1 octet per frame.
1
2 octets per frame.
10
3 octets per frame.
11
4 octets per frame.
0x405
K_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
K_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
00000
Default value.
11111
32 frames per multiframe.
0x406
M_REG
[7:0]
M_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x407
CS_N_REG
[7:6]
CS_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
5
RESERVED
Reserved.
0x0
R
[4:0]
N_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x408
NP_REG
[7:5]
SUBCLASSV_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
[4:0]
NP_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x409
S_REG
[7:5]
JESDV_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
000
JESD204A.
001
JESD204B.
[4:0]
S_RD_1
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x40A
HD_CF_REG
7
HD_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Low density mode.
1
High density mode.
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
CF_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x40B
RES1_REG
[7:0]
RES1_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x40C
RES2_REG
[7:0]
RES2_RD
Received ILAS configuration on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x40D
CHECKSUM0_REG
[7:0]
LL_FCHK0
Received checksum during ILAS on Lane 0.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R



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