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AD9174 Datasheet(PDF) 127 Page - Analog Devices |
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AD9174 Datasheet(HTML) 127 Page - Analog Devices |
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127 / 164 page  Data Sheet AD9174 Rev. A | Page 127 of 164 Addr. Name Bits Bit Name Settings Description Reset Access 0x43D CHECKSUM6_REG [7:0] LL_FCHK6 Received checksum during ILAS on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x43E COMPSUM6_REG [7:0] LL_FCMP6 Computed checksum on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x442 LID7_REG [7:5] RESERVED Reserved. 0x0 R [4:0] LL_LID7 Received ILAS LID configuration on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x445 CHECKSUM7_REG [7:0] LL_FCHK7 Received checksum during ILAS on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x446 COMPSUM7_REG [7:0] LL_FCMP7 Computed checksum on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x450 ILS_DID [7:0] DID Device (link) identification number. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W 0x451 ILS_BID [7:0] BID Bank ID, extension to DID. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 0x452 ILS_LID0 7 RESERVED Reserved. 0x0 R 6 ADJDIR Direction to adjust the DAC LMFC. Link information is received on Link Lane 0 as specified in Section 8.3 of JESD204B. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W 5 PHADJ Phase adjustment request to the DAC. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W [4:0] LID0 Lane identification number (within link). This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 0x453 ILS_SCR_L 7 SCR Scramble enabled for the link. This control is paged by the LINK_PAGE control in Register 0x300. 0x1 R/W 0 Descrambling is disabled. 1 Descrambling is enabled. [6:5] RESERVED Reserved. 0x0 R [4:0] L_1 Number of lanes per converter (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. 0x7 R/W 0x454 ILS_F [7:0] F_1 Number of octets per frame per lane (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R/W 0x455 ILS_K [7:5] RESERVED Reserved. 0x0 R [4:0] K_1 Number of frames per multiframe (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. 0x1F R/W 11111 32 frames per multiframe. |
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