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AD9174 Datasheet(PDF) 124 Page - Analog Devices |
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AD9174 Datasheet(HTML) 124 Page - Analog Devices |
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124 / 164 page  AD9174 Data Sheet Rev. A | Page 124 of 164 Addr. Name Bits Bit Name Settings Description Reset Access 0x32F SHORT_TPL_TEST_3 7 SHORT_TPL_LINK_ SEL For running STPL on dual-link JESD204B modes. Selects whether the STPL test is performed on samples that are addressed to the DAC0 channelizers/datapaths (Link 0), or the DAC1 channelizers/datapaths (Link 1). 0x0 R/W 0 Link 0 samples are tested. 1 Link 1 samples are tested. 6 SHORT_TPL_IQ_ SAMPLE_SEL Selects which data stream (path) to test for a complex subchannel of the channelizer, I or Q. For nonIQ JESD204B modes, select the I path. 0x0 R/W 0 Select to test the I data stream. 1 Select to test the Q data stream. [5:1] RESERVED Reserved. 0x0 R/W 0 SHORT_TPL_FAIL Short transport layer test fail. This bit shows if the selected DAC sample matches the expected sample for the short transport layer test. If they match, the test passes. Otherwise, the test fails. 0x0 R 0 Test pass. 1 Test fail. 0x334 JESD_BIT_INVERSE_ CTRL [7:0] JESD_BIT_INVERSE Logical lane invert. Each bit of this control inverses the JESD204B deserialized data from one specific JESD204B receiver PHY. Set Bit x high to invert the JESD204B deserialized data on Logical Lane x. 0x0 R/W 0x400 DID_REG [7:0] DID_RD Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x401 BID_REG [7:0] BID_RD Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x402 LID0_REG 7 RESERVED Reserved. 0x0 R 6 ADJDIR_RD Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 5 PHADJ_RD Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R [4:0] LL_LID0 Received ILAS LID configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0x403 SCR_L_REG 7 SCR_RD Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 0 Scrambling is disabled. 1 Scrambling is enabled. [6:5] RESERVED Reserved. 0x0 R [4:0] L_RD_1 Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 0x0 R 00000 1 lane per converter device. 00001 2 lanes per converter device. 00010 3 lanes per converter device. 00011 4 lanes per converter device. |
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