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AD9174 Datasheet(PDF) 126 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 126 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 126 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x40E
COMPSUM0_REG
[7:0]
LL_FCMP0
Computed checksum on Lane 0. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x412
LID1_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID1
Received ILAS LID configuration on Lane 1.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x415
CHECKSUM1_REG
[7:0]
LL_FCHK1
Received checksum during ILAS on Lane 1.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x416
COMPSUM1_REG
[7:0]
LL_FCMP1
Computed checksum on Lane 1. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x41A
LID2_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID2
Received ILAS LID configuration on Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x41D
CHECKSUM2_REG
[7:0]
LL_FCHK2
Received checksum during ILAS on Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x41E
COMPSUM2_REG
[7:0]
LL_FCMP2
Computed checksum on Lane 2. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x422
LID3_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID3
Received ILAS LID configuration on Lane 3.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x425
CHECKSUM3_REG
[7:0]
LL_FCHK3
Received checksum during ILAS on Lane 3.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x426
COMPSUM3_REG
[7:0]
LL_FCMP3
Computed checksum on Lane 3. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x42A
LID4_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID4
Received ILAS LID configuration on Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x42D
CHECKSUM4_REG
[7:0]
LL_FCHK4
Received checksum during ILAS on Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x42E
COMPSUM4_REG
[7:0]
LL_FCMP4
Computed checksum on Lane 4. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x432
LID5_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID5
Received ILAS LID configuration on Lane 5.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x435
CHECKSUM5_REG
[7:0]
LL_FCHK5
Received checksum during ILAS on Lane 5.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0x436
COMPSUM5_REG
[7:0]
LL_FCMP5
Computed checksum on Lane 5. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0x43A
LID6_REG
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
LL_LID6
Received ILAS LID configuration on Lane 6.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R



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