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AD9174 Datasheet(PDF) 128 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 128 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 128 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x456
ILS_M
[7:0]
M_1
Number of subchannels per link (minus 1).
This control is paged by the LINK_PAGE
control in Register 0x300.
0x1
R/W
0x457
ILS_CS_N
[7:6]
CS
Number of control bits per sample. Only
Link 0 is supported. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
5
RESERVED
Reserved.
0x0
R
[4:0]
N_1
Converter resolution (minus 1). This
control is paged by the LINK_PAGE control
in Register 0x300.
0xF
R/W
0x458
ILS_NP
[7:5]
SUBCLASSV
Device subclass version. This control is
paged by the LINK_PAGE control in
Register 0x300.
0x0
R/W
000
Subclass 0.
001
Subclass 1.
[4:0]
NP_1
Total number of bits per sample (minus 1).
This control is paged by the LINK_PAGE
control in Register 0x300.
0xF
R/W
0x459
ILS_S
[7:5]
JESDV
JESD204 version. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
000
JESD204A.
001
JESD204B.
[4:0]
S_1
Number of samples per converter per
frame cycle (minus 1). This control is paged
by the LINK_PAGE control in Register 0x300.
0x1
R/W
0x45A
ILS_HD_CF
7
HD
High density format, always set to 1. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x1
R
0
Low density mode.
1
High density mode.
[6:5]
RESERVED
Reserved.
0x0
R
[4:0]
CF
Number of control bits per sample. Only
Link 0 is supported. This control is paged
by the LINK_PAGE control in Register 0x300.
0x0
R
0x45B
ILS_RES1
[7:0]
RES1
Reserved field 1. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
0x45C
ILS_RES2
[7:0]
RES2
Reserved field 2. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
0x45D
ILS_CHECKSUM
[7:0]
FCHK0
Calculated link configuration checksum. This
control is paged by the LINK_PAGE control
in Register 0x300. This signal must only be
programmed while the QBD is held in soft
reset (Register 0x475, Bit 3), and must not
be changed during normal operation.
0x0
R/W
0x46C
LANE_DESKEW
7
ILD7
Interlane deskew status for Lane 7. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
6
ILD6
Interlane deskew status for Lane 6. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.



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