AD9174 datasheet(119/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 119 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x307

LMFC_VAR_1

[7:6]

RESERVED

Reserved.

0x0

[5:0]

LMFC_VAR_1

Variable delay buffer, Link 1. These bits set

when data is read from a buffer to be con-

sistent across links and power cycles (in units

of PCLK cycles). The maximum value is 0xC.

0x3F

R/W

0x308

XBAR_LN_0_1

[7:6]

RESERVED

Reserved.

0x0

[5:3]

LOGICAL_LANE1_

SRC

Logical Lane 1 source. These bits select a

physical lane to be mapped onto Logical

Lane 1.

0x1

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

[2:0]

LOGICAL_LANE0_

SRC

Logical Lane 0 source. These bits select a

physical lane to be mapped onto Logical

Lane 0.

0x0

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

0x309

XBAR_LN_2_3

[7:6]

RESERVED

Reserved.

0x0

[5:3]

LOGICAL_LANE3_

SRC

Logical Lane 3 source. These bits select a

physical lane to be mapped onto Logical

Lane 3.

0x3

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

[2:0]

LOGICAL_LANE2_

SRC

Logical Lane 2 source. These bits select a

physical lane to be mapped onto Logical

Lane 2.

0x2

R/W

000

Data is from SERDIN0±.

001

Data is from SERDIN1±.

010

Data is from SERDIN2±.

011

Data is from SERDIN3±.

100

Data is from SERDIN4±.

101

Data is from SERDIN5±.

110

Data is from SERDIN6±.

111

Data is from SERDIN7±.

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