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AD9174 Datasheet(PDF) 146 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 146 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 146 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0
CGS1
Code group synchronization status for
Lane 1. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0x4B2
LINK_STATUS2
7
BDE2
Bad disparity errors status for Lane 2. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
6
NIT2
Not in table errors status for Lane 2. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
5
UEK2
Unexpected K character errors status for
Lane 2. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
4
ILD2
Interlane deskew status for Lane 2. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
3
ILS2
Initial lane synchronization status for Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
2
CKS2
Computed checksum status for Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Checksum is incorrect.
1
Checksum is correct.
1
FS2
Frame synchronization status for Lane 2.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0
CGS2
Code group synchronization status for
Lane 2. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.



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