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AD9174 Datasheet(PDF) 148 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 148 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 148 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
4
ILD4
Interlane deskew status for Lane 4. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
3
ILS4
Initial lane synchronization status for Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
2
CKS4
Computed checksum status for Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Checksum is incorrect.
1
Checksum is correct.
1
FS4
Frame synchronization status for Lane 4.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0
CGS4
Code group synchronization status for
Lane 4. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0x4B5
LINK_STATUS5
7
BDE5
Bad disparity errors status for Lane 5. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
6
NIT5
Not in table errors status for Lane 5. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
5
UEK5
Unexpected K character errors status for
Lane 5. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
4
ILD5
Interlane deskew status for Lane 5. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
3
ILS5
Initial lane synchronization status for Lane 5.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
2
CKS5
Computed checksum status for Lane 5.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Checksum is incorrect.
1
Checksum is correct.



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