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AD9174 Datasheet(PDF) 150 Page - Analog Devices

Part # AD9174
Description  Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
PDF  164 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9174 Datasheet(HTML) 150 Page - Analog Devices

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AD9174
Data Sheet
Rev. A | Page 150 of 164
Addr.
Name
Bits
Bit Name
Settings
Description
Reset
Access
0x4B7
LINK_STATUS7
7
BDE7
Bad disparity errors status for Lane 7. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
6
NIT7
Not in table errors status for Lane 7. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
5
UEK7
Unexpected K character errors status Lane 7.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Error count < ETH[7:0] value.
1
Error count ≥ ETH[7:0] value.
4
ILD7
Interlane deskew status for Lane 7. This
control is paged by the LINK_PAGE control
in Register 0x300.
0x0
R
0
Deskew failed.
1
Deskew achieved.
3
ILS7
Initial lane synchronization status for Lane 7.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
2
CKS7
Computed checksum status for Lane 7.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Checksum is incorrect.
1
Checksum is correct.
1
FS7
Frame synchronization status for Lane 7.
This control is paged by the LINK_PAGE
control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0
CGS7
Code group synchronization status for
Lane 7. This control is paged by the
LINK_PAGE control in Register 0x300.
0x0
R
0
Synchronization lost.
1
Synchronization achieved.
0x4B8
JESD_IRQ_ENABLEA
7
EN_BDE
Bad disparity error counter. This control is
paged by the LINK_PAGE control in
Register 0x300.
0x0
R/W
6
EN_NIT
Not in table error counter. This control is
paged by the LINK_PAGE control in
Register 0x300.
0x0
R/W
5
EN_UEK
Unexpected K error counter. This control is
paged by the LINK_PAGE control in
Register 0x300.
0x0
R/W
4
EN_ILD
Interlane deskew. This control is paged by
the LINK_PAGE control in Register 0x300.
0x0
R/W
3
EN_ILS
Initial lane synchronization. This control is
paged by the LINK_PAGE control in
Register 0x300.
0x0
R/W



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