AD9174 datasheet(154/164 Pages) AD

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AD9174

Data Sheet

Rev. A | Page 154 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

0x58B

SHORT_PA_POWER_

LSB

[7:0]

SHORT_PA_

POWER[7:0]

Short average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0

0x58C

SHORT_PA_POWER_

MSB

[7:5]

RESERVED

Reserved.

0x0

[4:0]

SHORT_PA_

POWER[12:8]

Short average power readback. Power

detected at data bus = I2 + Q2. The data

bus calculation only uses the 6 MSBs of the

I and Q data bus samples. This control is

paged by the MAINDAC_PAGE control in

0x0

0x58D

TXEN_SM_0

[7:1]

RESERVED

Reserved.

0x1

R/W

ENA_TXENSM

Enable TXEN state machine. This control is

paged by the MAINDAC_PAGE control in

0x0

R/W

0x596

BLANKING_CTRL

[7:4]

RESERVED

Reserved.

0x0

SPI_TXEN

If ENA_SPI_TXEN (Bit 2 of this register) = 1,

the value of this register is the value of the

TXENx status. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0

R/W

ENA_SPI_TXEN

Enable TXENx control via the SPI by setting

this bit to 1. This control is paged by the

MAINDAC_PAGE control in Register 0x008.

0x0

R/W

[1:0]

RESERVED

Reserved.

0x0

0x597

JESD_PA_INT0

[7:0]

JESD_PA_INT_

CNTRL[7:0]

Each bit enables a JESD204B PA interrupt.

0x0

R/W

Bit 8 = CGS.

Bit 7 = frame sync.

Bit 6 = good check sum.

Bit 5 = initial lane sync.

Bit 4 = interlane deskew.

Bit 3 = bad disparity error counter.

Bit 2 = NIT error counter.

Bit 1= UEK error counter.

Bit 0 = lane FIFO overflow or underflow.

0x598

JESD_PA_INT1

[7:1]

RESERVED

Reserved.

0x0

JESD_PA_INT_

CNTRL[8]

Each bit enables a JESD204B PA interrupt.

0x0

R/W

Bit 8 = CGS

Bit 7 = frame sync.

Bit 6 = good check sum.

Bit 5 = initial lane sync.

Bit 4 = interlane deskew.

Bit 3 = bad disparity error counter.

Bit 2 = NIT error counter.

Bit 1= UEK error counter.

Bit 0 = lane FIFO overflow or underflow.

0x599

TXEN_FLUSH_CTRL0

[7:1]

RESERVED

Reserved.

0x0

SPI_FLUSH_EN

Enable datapath flush. This control is

paged by the MAINDAC_PAGE control in

0x1

R/W

0x705

NVM_LOADER_EN

[7:1]

RESERVED

Reserved.

0x0

NVM_BLR_EN

Enable bootloader. This bit self clears when

the boot loader completes or fails.

0x0

R/W

AD9174 Datasheet(PDF) 154 Page - Analog Devices

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