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AD9174 Datasheet(PDF) 155 Page - Analog Devices |
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AD9174 Datasheet(HTML) 155 Page - Analog Devices |
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155 / 164 page  Data Sheet AD9174 Rev. A | Page 155 of 164 Addr. Name Bits Bit Name Settings Description Reset Access 0x790 DACPLL_PDCTRL0 7 PLL_PD5 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W [6:4] PLL_PD4 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 3 PLL_PD3 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value default (0). 0x0 R/W 2 PLL_PD2 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 1 PLL_PD1 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, write this bit to 0. 0x1 R/W 0 PLL_PD0 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 0x791 DACPLL_PDCTRL1 [7:5] RESERVED Reserved. 0x0 R/W 4 PLL_PD10 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 3 PLL_PD9 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 2 PLL_PD8 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 1 PLL_PD7 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 0 PLL_PD6 PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). 0x0 R/W 0x792 DACPLL_CTRL0 [7:2] RESERVED Reserved. 0x0 R 1 D_CAL_RESET Resets VCO calibration. 0x1 R/W 0 D_RESET_VCO_DIV Setting this high holds the VCO output divider in reset. This has the effect of turning off the input (and output) of the ADC clock driver. 0x0 R/W 0x793 DACPLL_CTRL1 [7:2] RESERVED Reserved. 0x0 R [1:0] M_DIVIDER−1 Programmable predivider value for PFD (in n − 1 notation). M_DIVIDER = PLL reference clock/PFD frequency. For optimal spectral performance, choose an M divider setting that selects a high PFD frequency within the allowable PFD range. 0x0 R/W 0 Divide by 1. 1 Divide by 2. 10 Divide by 3. 11 Divide by 4. 0x794 DACPLL_CTRL2 [7:6] RESERVED Reserved. 0x0 R/W [5:0] DACPLL_CP Charge pump current control. Charge pump current = 100 µA + code × 100 µA. 0x4 R/W 0x795 DACPLL_CTRL3 [7:4] RESERVED Reserved. 0x0 R/W [3:0] D_CP_CALBITS DAC PLL optimization control. 0x8 R/W 0x796 DACPLL_CTRL4 [7:4] PLL_CTRL0 DAC PLL optimization control. 0xD R/W |
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