AD9174 datasheet(151/164 Pages) AD

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Data Sheet

AD9174

Rev. A | Page 151 of 164

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

EN_CKS

Good checksum. This bit compares two

checksums: the checksum that the trans-

mitter sent over the link during the ILAS

and the checksum that the receiver

calculated from the ILAS data that the

transmitter sent over the link. The checksum

IRQ only looks at data sent by the trans-

mitter and not the checksum programmed

into Register 0x45D. This control is paged

by the LINK_PAGE control in Register 0x300.

0x0

R/W

EN_FS

Frame synchronization. This control is

paged by the LINK_PAGE control in

0x0

R/W

EN_CGS

Code group synchronization. This control

is paged by the LINK_PAGE control in

0x0

R/W

0x4B9

JESD_IRQ_ENABLEB

[7:1]

RESERVED

Reserved.

0x0

EN_ILAS

Configuration mismatch (checked for Lane 0

only). The ILAS IRQ compares the two sets

of ILAS data obtained by the receiver. The

first set of data is the ILAS data sent over

the JESD204B link by the transmitter. The

second set of data is the ILAS data

programmed into the receiver via the SPI

(Register 0x450 to Register 0x45D). If any

of the data differs, the IRQ is triggered. All

of the ILAS data, including the checksum,

is compared. This control is paged by the

LINK_PAGE control in Register 0x300.

0x0

R/W

0x4BA

JESD_IRQ_STATUSA

IRQ_BDE

Bad disparity error counter. This control is

paged by the LINK_PAGE control in

0x0

R/W

IRQ_NIT

Not in table error counter. This control is

paged by the LINK_PAGE control in

0x0

R/W

IRQ_UEK

Unexpected K error counter. This control is

paged by the LINK_PAGE control in

0x0

R/W

IRQ_ILD

Interlane deskew. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0

R/W

IRQ_ILS

Initial lane synchronization. This control is

paged by the LINK_PAGE control in

0x0

R/W

IRQ_CKS

Good checksum. This control is paged by

the LINK_PAGE control in Register 0x300.

0x0

R/W

IRQ_FS

Frame synchronization. This control is

paged by the LINK_PAGE control in

0x0

R/W

IRQ_CGS

Code group synchronization. This control

is paged by the LINK_PAGE control in

0x0

R/W

0x4BB

JESD_IRQ_STATUSB

[7:1]

RESERVED

Reserved.

0x0

IRQ_ILAS

Configuration mismatch (checked for Lane 0

only). This control is paged by the LINK_PAGE

control in Register 0x300.

0x0

R/W

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