PCI1031 datasheet(35/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PCI suspend/resume (continued)

NotOnResume

SUSPEND

PCIRESET

SUSPEND (high)

Power Up

Active

Suspend

Active

Needs SUSPEND

Does Not Need SUSPEND

Figure 9. PCI Reset and Suspend Mode

PC Card16 mode

When a 16-bit legacy PC Card is inserted into a socket, there are two options for minimizing power consumption.

The first is to use the card output enable (COE) bit (see bit 7 of the

ExCA power control register). When bit 7

is set, the outputs on the PC Card socket are placed in the high-impedance state. Bit 7 is software controlled.

Socket services must clear bit 7 to activate the socket. The second method is to set the power-down bit (see

bit 0 of the

ExCA global control register). When bit 0 is set, it enables an automated COE bit. When a card access

to a PC Card16 card is complete, the PCI1031 automatically places the card outputs in the high-impedance

state. When there is any activity on the socket, the outputs are automatically enabled.

The major difference between the use of the COE bit and the POWERDWN bit is that the COE bit resets the

PC Card16 PC Card and the POWERDWN bit does not. The POWERDWN bit continues to drive the Card

RESET line inactive, while the COE bit puts the RESET line in the high-impedance state.

PCI configuration header registers

A number of registers found in the PCI1031 PCI configuration space are defined in the PCI-to-PCI bridge

architecture specification revision 1.0, which, in turn, are common to the PCI local bus specification revision 2.1.

Registers common to both specifications are the device ID, vendor ID, status, command, class code, revision

ID, BIST, header type, latency timer, cache line size, interrupt pin, and interrupt line registers.

The following PCI specific registers listed in the previous paragraph are applicable to the entire device and are

not specific to any one PCI function (i.e., PC Card socket) on the PCI1031. These registers include the

device ID, vendor ID, status, command, class code, revision ID, BIST, header type, latency timer, cache line

size, interrupt pin, and interrupt line registers. Each register is mapped to the same location in both PCI

configuration spaces. Access is possible by addressing the configuration space of either function, but host

software should consistently access PCI specific registers through a single function. Detailed descriptions of

the PCI specific registers follow and are listed in Table 12. Most of the registers are implemented in the PCI1031

as defined in either the PCI local bus specification revision 2.1, the PCI-to-PCI bridge architecture specification

revision 1.0, or the Yenta specification revision 2.1. References to these documents are made where

appropriate. Additional register bits defined in the bridge control register (see

bridge control) enable features

specific to CardBus memory windows.

PCI1031 Datasheet(PDF) 35 Page - Texas Instruments

PCI1031 Datasheet(HTML) 35 Page - Texas Instruments

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