PCI1031 datasheet(95/100 Pages) TI

95 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PC Card cycle timing

The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and

I/O window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address

setup and hold times and the PC Card command active (low) interval. This allows the cycle generator to output

PC Card cycles that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding

the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput.

The PC Card address setup and hold times are a function of the wait-state bits. Table 49 shows address setup

time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 50 and Table 51 show command active

time in PCLK cycles and nanoseconds for I/O and memory cycles. Table 52 shows address hold time in PCLK

cycles and nanoseconds for I/O and memory cycles.

Table 49. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles

WAIT-STATE BITS

TS1 – 0 = 01

(PCLK/ns)

I/O

3/90

Memory

WS1

2/60

Memory

WS1

4/120

Table 50. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles

WAIT-STATE BITS

TS1 – 0 = 01

ZWS

(PCLK/ns)

19/570

I/O

23/690

7/210

19/570

23/690

Memory

23/690

7/210

Table 51. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles

WAIT-STATE BITS

TS1 – 0 = 01

ZWS

(PCLK/ns)

7/210

I/O

11/330

N/A

9/270

13/390

Memory

17/510

23/630

5/150

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