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PCI1031 Datasheet(PDF) 23 Page - Texas Instruments

Part # PCI1031
Description  PCI-TO-PC CARD16 CONTROLLER UNIT
PDF  100 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI1031 Datasheet(HTML) 23 Page - Texas Instruments

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PCI1031
PCI-TO-PC CARD16 CONTROLLER UNIT
SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997
23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
functional and CSC interrupts
Functional interrupts are defined as requests from a PC Card for interrupt service, and are indicated by asserting
specially defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards.
CSC interrupts are defined as events at the PC Card interface that are detected by the PCI1031 and can warrant
notification of host software for service. Such events include transitions on certain PC Card signals or card
removal/insertion. The specific examples of functional and CSC interrupts depend on the type of PC Card(s)
installed in the socket at any given time. The 16-bit interrupt sources differ between memory and I/O PC Cards.
Table 7 summarizes the sources of interrupts and the type of PC Card associated with them. The functional
interrupt events are valid only for 16-bit I/O Cards. Card insertion and removal events are independent of the
card type since the same card-detect signals are used in both cases and the PCI1031 cannot distinguish
between card types upon card insertion.
Table 7. PC Card Interrupt Events and Description
CARD TYPE
EVENT
TYPE
SIGNAL
DESCRIPTION
Battery conditions
CSC
BVD1(STSCHG)
A transition on BVD1 indicates a change in the PC Card
battery conditions.
16-bit memory
y
(BVD1, BVD2)
CSC
BVD2(SPKR)
A transition on BVD2 indicates a change in the PC Card
battery conditions.
Wait states
(READY)
CSC
READY(IREQ)
A transition on READY indicates a change in the ability of the
memory PC Card to accept or provide data.
16 bit I/O
Change in card status
(STSCHG)
CSC
BVD1(STSCHG)
The assertion of STSCHG indicates a status change on the
PC Card.
16-bit I/O
Interrupt request
(IREQ)
Functional
READY(IREQ)
The assertion of IREQ indicates an interrupt request from
the PC Card.
All PC Cards
Card insertion
or removal
CSC
CD1//CCD1,
CD2//CCD2
A transition on either CD1 // CCD1 or CD2 // CCD2 indicates
an insertion or removal of a 16-bit // CardBus PC Card.
All PC Cards
Power cycle complete
CSC
N/A
An interrupt is generated when a PC Card power up cycle
is complete.
The signal-naming convention for PC Card signals describes the function for 16-bit memory and I/O cards. The
16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The
16-bit I/O cards use two signal lines to signal interrupts: one to indicate a change in card status and another
dedicated to request interrupt servicing from the host. A 16-bit memory PC Card uses the BVD1 and BVD2
signals to indicate changes in battery conditions on the card, and it uses the READY signal to insert wait states
during memory card data transfers.
The PC Card standard describes the power-up sequence that must be followed by the PCI1031 when an
insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this
power-up sequence, the PCI1031 interrupt scheme can be used to notify the host system denoted by “power
cycle complete” (see Table 7). This interrupt source is considered a PCI1031 internal event because it does not
depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket.
Host software can individually mask (disable) each of the potential CSC interrupt sources listed in Table 7 by
setting the appropriate bits in the PCI1031. By individually masking the interrupt sources listed in Table 7, host
software can control which events cause a PCI1031 interrupt. Host software has some control over which
system interrupt the PCI1031 asserts by programming the appropriate routing registers. The PCI1031 allows
host software to route PC Card CSC and functional interrupts to separate system interrupts. Interrupt routing
is specific to the interrupt signaling method used and is discussed in the following sections.



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