PCI1031 datasheet(46/100 Pages) TI

46 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

bridge control register

Bit

Name

Bridge control

Type

R/W

Default

Bridge control

Type:

Read only, read/write (see individual bit descriptions)

Offset:

3Eh

Default:

0340h

Description: This register provides control over PCI1031 bridging functions. Refer to Table 15 for a

complete description of the register contents.

Table 15. Bridge Control Register

BIT

TYPE

FUNCTION

15–11

Reserved. Bits 15–11 are read only and return 0s when read. Writes have no effect.

R/W

Write posting enable. Enables posting of write data to and from the socket. If bit 10 is not set, the bridge must drain any

data in its buffers before accepting data for or from the socket. Each data word must then be accepted by the target before

the bridge can accept the next word from the source master. The bridge must not release the source master until the last

word is accepted by the target. Operating with write posting disabled inhibits system performance. Bit 10 is encoded as:

0 = Write posting is disabled (default).

1 = Write posting is enabled.

R/W

Memory window 1 type (nonfunctional)

R/W

Memory window 0 type (nonfunctional)

R/W

PCI interrupt-IREQ routing enable bit. When bit 7 is 0 and the PCI interrupt bit in device control register (see

device control

register) is enabled, the functional card interrupts are routed to the PCI interrupt for the socket (INTA or INTB). When bit

7 is 1, the functional card interrupt is routed to an IRQ pin using the routing selected in the ExCA card interrupt and general

control register (see

ExCA interrupt and general control register). Bit 7 is encoded as:

0 = Functional interrupts are routed to PCI interrupts (default).

1 = Functional interrupts are routed by ExCA registers.

R/W

CardBus reset (nonfunctional)

R/W

Master abort mode. Bit 5 controls how the PCI1031 responds to a master abort when the PCI1031 is a master. Bit 5 is

common between each socket. Bit 5 is encoded as:

0 = Master aborts not reported (default)

1 = Signal target abort and SERR, if enabled

Reserved. Bit 4 is read only and returns 0, when read. Writes have no effect.

R/W

VGA enable. Bit 3 affects how the PCI1031 responds to VGA addresses. Bit 3 is encoded as:

0 = Normal operation. Accesses to VGA addresses are forwarded (default).

1 = Accesses to VGA addresses are not forwarded.

R/W

Reserved. Bit 2 is nonfunctional.

R/W

SERR enable (nonfunctional)

R/W

Parity error response enable (nonfunctional)

PCI1031 Datasheet(PDF) 46 Page - Texas Instruments

PCI1031 Datasheet(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL