PCI1031 datasheet(49/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 16. System Control Register (Continued)

BIT

TYPE

FUNCTION

Reserved. Bit 12 is read only and returns 1 when read.

Power stream in progress status bit. When high, bit 11 indicates that a power stream to the TPS2206 is in progress and

power requested. Bit 11 is cleared when the power stream is finished. This is a global bit. Bit 11 is encoded as:

0 = No power stream in progress

1 = Power stream in progress

Power-down delay in progress status bit. When high, bit 10 indicates that a power-down stream is sent to the TPS2206

but power is not yet stable. Bit 10 is cleared when the power-down delay expires. This is a global bit. Bit 10 is encoded

as:

0 = Power-down delay not in effect

1 = Power-down delay in effect

Power-up delay in progress status bit. When high, bit 9 indicates that a power-up stream is sent to the TPS2206 but power

is not yet stable. Bit 9 is cleared when the power-up delay expires. This is a global bit. Bit 9 is encoded as:

0 = Power-up delay not in effect

1 = Power-up delay in effect

Interrogation in progress status. When high, bit 8 indicates an interrogation is in progress. Bit 8 is cleared when the

interrogation is complete. Bit 8 is encoded as:

0 = Interrogation not in progress

1 = Interrogation in progress

7–6

Reserved. Bits 7–6 are read only and return 0s when read. Writes have no effect.

R/W

ExCA identification and revision register read only enable. When bit 5 is set, the entire ExCA identification and revision

0 = ExCA identification and revision register are read/write.

1 = ExCA identification and revision register are read only (default).

R/W

CardBus data parity SERR signaling enable bit (nonfunctional)

R/W

PC/PCI DMA enable bit. Enables PC/PCI DMA. When enabled, the PC/PCI DMA request is output on IRQ7 and the

PC/PCI DMA grant is input on IRQ11. This is a global bit. Bit 3 is encoded as:

0 = PC/PCI DMA disabled (default)

1 = PC/PCI DMA enabled

R/W

Asynchronous interrupt mode enable bit. When enabled, bit 2 allows asynchronous card status-change events to cause

an interrupt without the PCI clock running. The only card status-change interrupt that requires a clock in this mode is the

power status, since a clock is required to send the power stream to the TPS2206. This is a global bit. Bit 2 is encoded

as:

0 = Asynchronous interrupt mode disabled (default)

1 = Asynchronous interrupt mode enabled

R/W

Keep clock. Keep PCI clock running bit. When bit 1 is set (keep clock run enabled) and PCI clock run is enabled (bit 0

is set), the PCI1031 requests that the PCI clock continue running in response to PCI clock run deassertion. If bit 1 is

cleared, the internal status of the PCI1031 determines if the clock can be stopped. This is a global bit. Bit 1 is encoded

as:

0 = Keep PCI clock running disabled (default)

1 = Keep PCI clock running enabled

R/W

PCI clock run enable. When enabled, bit 0 defines IRQ10/CLKRUN as the PCI clock run pin and allows the PCI1031 to

support PCI CLKRUN. When bit 0 is cleared, the PCI1031 ignores the PCI CLKRUN signal. This is a global bit. Bit 0 is

encoded as:

0 = PCI clock run disabled (default)

1 = PCI clock run enabled

PCI1031 Datasheet(PDF) 49 Page - Texas Instruments

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