PCI1031 datasheet(37/100 Pages) TI

37 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PCI configuration headers (continued)

Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers.

Socket DMA register 0 applies to the PC Card portion of DMA transfers. Socket DMA register 1 applies to the

PCI portion of DMA transfers specifically to set up the DMA support required in distributed DMA. Socket DMA

interface and the PCI interface.

Descriptions of each of the registers follow. Before writing data to any of the TI extension registers, host software

must first read the register to preserve the current contents. After reading the register, software can modify the

desired bits and write back the new data. This preserves current register settings and prevents unpredictable

or undesirable behavior.

The PCI1031 configuration header is shown in Table 12.

Table 12. PCI1031 Configuration Header

OFFSET

Device ID

Vendor ID

00h

Status

Command

04h

Class code

Revision ID

08h

BIST

Header type

Latency timer†

Cache line size†

0Ch

CardBus socket registers/ExCA base-address register

10h

Secondary status (unused)‡

Reserved

14h

CardBus latency timer†

Subordinate bus number

CardBus bus number

PCI bus number†

18h

CardBus memory base register 0 (unused)‡

1Ch

CardBus memory limit register 0 (unused)‡

20h

CardBus memory base register 1 (unused)‡

24h

CardBus memory limit register 1 (unused)‡

28h

CardBus I/O base register 0 (unused)‡

2Ch

CardBus I/O limit register 0 (unused)‡

30h

CardBus I/O base register 1 (unused)‡

34h

CardBus I/O limit register 1 (unused)‡

38h

Bridge control†

Interrupt pin

Interrupt line

3Ch

Subsystem ID

Subsystem vendor ID

40h

PC Card 16-Bit I/F legacy-mode base address†

44h

Reserved

48h–7Ch

System control†

80h

Reserved

84h–8Ch

Test†

Device control†

Card control†

Retry status†

90h

Socket DMA register 0

94h

Socket DMA register 1

98h

Reserved

9Ch–FFh

† One or more bits in the register are common to PCI functions 0 and 1.

‡ Unused registers are read only.

PCI1031 Datasheet(PDF) 37 Page - Texas Instruments

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