PCI1031 datasheet(73/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA global control register (index 1Eh)

Bit

Name

ExCA global control

Type

R/W

Default

ExCA global control

Type:

Read only, read/write (see individual bit descriptions)

Offset:

CardBus socket address + 81Eh; Card A ExCA offset 1Eh

Card B ExCA offset 5Eh

Default:

00h

Description: This register controls both PC Card sockets and is not duplicated for each socket. The host

interrupt mode bits in this register (retained for Intel 82365SL-DF compatibility) must also

agree with the interrupt mode registers found in the TI extension registers. Host software is

responsible for maintaining coherence between these registers. Refer to Table 36 for a

complete description of the register contents.

Table 36. ExCA Global Control Register (Index 1Eh)

BIT

TYPE

FUNCTION

7–5

Reserved. Bits 7–5 are read only and return 0s when read.

R/W

Level/edge interrupt mode select – Card B. Bit 4 selects the signaling mode for the PCI1031 host interrupt for Card B

interrupts. Bit 4 is encoded as:

0 = Host interrupt is in edge mode (default).

1 = Host interrupt is in level mode.

R/W

Level/edge interrupt mode select – Card A. Bit 3 selects the signaling mode for the PCI1031 host interrupt for Card A

interrupts. Bit 3 is encoded as:

0 = Host interrupt is in edge mode (default).

1 = Host interrupt is in level mode.

R/W

Interrupt flag clear mode select. Bit 2 selects explicit writeback of card status-change interrupt acknowledges. Bit 2 is

encoded as:

0 = Card status-change interrupt flags are cleared by a read of the ExCA card status-change register

(default).

1 = Card status-change interrupt flags are cleared by an explicit writeback of 1 to the card status-change

R/W

Card status-change level/edge mode select. Bit 1 selects the signaling mode for the PCI1031 host interrupt for card status

changes. Bit 1 is encoded as:

0 = Host interrupt is in edge mode (default).

1 = Host interrupt is in level mode.

R/W

PWRDWN mode select. When bit 0 is set to 1, the PCI1031 is in power-down mode. In power-down mode, the PCI1031

outputs are driven to the high-impedance state until an active cycle is executed on the card interface. Following an active

cycle, the outputs are again placed in a high-impedance state. The PCI1031 still receives DMA requests, functional

interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the interface. Bit

0 is encoded as:

0 = Power-down mode is disabled (default).

1 = Power-down mode is enabled.

PCI1031 Datasheet(PDF) 73 Page - Texas Instruments

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