PCI1031 datasheet(7/100 Pages) TI

7 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

PCI system

TERMINAL

I/O

FUNCTION

NAME

NO.

TYPE

FUNCTION

PCLK

165

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising

edge of PCLK.

RSTIN

166

PCI reset. When the RSTIN signal is asserted low, the PCI1031 forces all output buffers to the high-impedance

state and resets all internal registers. When asserted, the PCI1031 is nonfunctional. After RSTIN is deasserted,

the PCI1031 returns to the default state. When the PCI1031 SUSPEND mode is enabled, the device is protected

from any RSTIN reset (i.e., the PCI1031 internal register contents are preserved). See

power management.

PCI address and data

TERMINAL

I/O

FUNCTION

NAME

NO.

TYPE

FUNCTION

AD31

AD30

AD29

AD28

AD27

AD26

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD18

AD17

AD16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

170

171

173

174

176

177

178

179

183

184

185

186

188

189

190

191

204

205

206

208

I/O

Address/data bus. AD31–AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI

cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0

contain data.

C/BE3

C/BE2

C/BE1

C/BE0

180

192

203

I/O

Bus commands and byte enables. C/BE3–C/BE0 are multiplexed on the same PCI terminals. During the address

phase, C/BE3–C/BE0 define the bus command. During the data phase, C/BE3–C/BE0 are used as byte enables.

The byte enables determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1

applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).

PAR

202

I/O

Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1031 calculates

even parity across the AD and C/BE buses and outputs the results on PAR, delayed by one clock.

PCI1031 Datasheet(PDF) 7 Page - Texas Instruments

PCI1031 Datasheet(HTML) 7 Page - Texas Instruments

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