PCI1031 datasheet(24/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

functional and CSC interrupts (continued)

When an interrupt is signaled by the PCI1031, the interrupt service routine must be able to discern which of the

events in Table 8 caused the interrupt. This is of particular interest with CSC interrupts, where a variety of events

at the card interface can cause interrupts. Internal registers in the PCI1031 provide flags that report to the host

interrupt service routine which of the interrupt sources was the cause of an interrupt. By first reading these status

bits, the interrupt service routine can determine which action to take.

Table 8 describes the valid PC Card interrupt events and details the internal PCI1031 registers associated with

masking and reporting them.

Table 8. PC Card Interrupt Mask and Flag Registers

CARD TYPE

EVENT

MASK

FLAG

16-bit memory

Battery conditions

(BVD1, BVD2)

ExCA offset 05h/45h/805h, Bits 1 and 0

ExCA offset 04h/44h/804h, Bits 1 and 0

Wait states (READY)

ExCA offset 05h/45h/805h, Bit 2

ExCA offset 04h/44h/804h, Bit 2

16 bit I/O

Change in card status

(STSCHG)

ExCA offset 05h/45h/805h, Bit 0

Always enabled

ExCA offset 04h/44h/804h, Bit 0

16-bit I/O

Interrupt request (IREQ)

Power cycle complete

Always enabled

PCI configuration offset 91h, Bit 0

All PC Cards

Card insertion or removal

Socket mask register, Bits 2 and 1

Socket event register, Bits 2 and 1

ExCA offset 04h/44h/804h, Bit 3

There are various methods of clearing the interrupt flag bit. ExCA provides two methods to clear 16-bit

PC Card-related interrupt flags. One is a write of 1 to the bit in question, and the other is a read from the register.

This selection is made by bit 2 in ExCA offset 1Eh/5Eh/81Eh (see

ExCA I/O window 0–1 offset-address

high-byte register).

There is a single exception to Table 8, when PCI interrupt signaling is used. The enable/disable bits for

functional and CSC interrupts are found in separate registers in PCI configuration register 91h, bits 4 and 3 (see

card control register). Refer to the section on PCI interrupt signaling for details.

ISA IRQ interrupts

NOTE:

All unused interrupt pins should be pulled high by a 43-k

Ω resistor.

Among the PCI1031 interrupt signaling schemes is the traditional ISA IRQ signaling, available in most x86 PCs.

Dedicated terminals on the PCI1031 can be used to assert 10 of the 15 ISA IRQs: IRQ3, IRQ4, IRQ5, IRQ7,

IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, and IRQ15. These IRQs represent the common interrupts expected by

PC Card applications and several free IRQs for CSC routing.

In a system using ISA IRQs, the host software must first configure the PCI1031 to use ISA signaling by setting

bits 2–1 of PCI configuration register, offset 92h, to 01b (see

device control register). The ten IRQ terminals

remain in the high-impedance state until the ExCA Card CSC and functional interrupt routing registers are set

to a valid state. The step-by-step series of events that host software must follow to successfully configure the

PCI1031 for ISA IRQ signaling follows. These steps assume that the system has powered up and RSTIN is high

(deasserted). In cases where only selected bits of a register are to be modified, host software must leave the

remaining register bits unchanged by reading the current contents of the register first, modifying the desired bits,

then writing the new value back to the respective PCI1031 register.

PCI1031 Datasheet(PDF) 24 Page - Texas Instruments

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