PCI1031 datasheet(27/100 Pages) TI

27 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

serialized IRQ signaling (continued)

Set bits 2–1 of PCI device control register 92h (function 0) to 10b.

Write to the upper nibble of ExCA register 05h/45h/805h for desired CSC routing for each socket (all 15 IRQs

are available for routing when serialized IRQ signaling has been selected).

If a PC Card is installed in the socket and requires functional interrupts, write to the lower nibble of ExCA

Using Table 8, write to the appropriate mask register bits to enable interrupt generation for desired events.

On card-removal events, host software should unroute any functional interrupts that were set for that

socket.

Upon card-insertion events, host software should reconfigure the mask and routing registers to support the

new card requirements.

PCI clock run

The PCI1031 supports PCI clock run (CLKRUN). CLKRUN is an optional signal that is used as an input to

determine the status of CLK as an open-drain output to request the CLK to restart or to speed up. PCI CLKRUN

is enabled by setting bit 0 in the system control register (see

system control register). When the PCI clock

resource manager informs the PCI1031 that the PCI clock is stopped or slowed, the PCI1031 ensures that no

transactions are in progress for either of the two PC Card sockets before allowing the clock resource manager

to stop or slow the PCI clock. CLKRUN shares the IRQ10 pin on the PCI1031. See

system control register for

information on configuring the clock run option.

CLKRUN configuration

Bits 1–0 in the TI extension registers at offset 80h are used to enable and configure CLKRUN. Bit 0 enables

CLKRUN. Bit 1, when set, keeps the PCI clock running in response to a PCI CLKRUN deassertion (see

system

control register).

conditions for stopping/slowing the PCI clock

Before allowing the central resource to slow or stop the PCI clock, the following conditions are checked:

D The PCI CLKRUN enable bit is set and the KEEP CLOCK bit is cleared (see system control register, bit 1).

D Neither socket is in the process of powering up or powering down.

D The 16-bit resource managers are not busy.

D The PCI master is not busy.

D No socket interrogation is underway.

D No card interrupts are pending.

conditions for restarting the PCI clock

The PCI clock restarts when any PC Card is installed in a socket or removed from a socket. For 16-bit cards,

if the PCI clock stops or slows, the PCI1031 requests that the clock be restarted under the following conditions:

D A 16-bit I/O card asserts IREQ.

D A 16-bit I/O card asserts STSCHG/RI.

D A 16-bit DMA card asserts DREQ.

PCI1031 Datasheet(PDF) 27 Page - Texas Instruments

PCI1031 Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL