PCI1031 datasheet(28/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PC Card DMA and distributed DMA

DMA is a concept with many different interpretations and implementations, depending on the context and

application. In fact, DMA support within the PCI1031 has different connotations, depending on whether the

subject is PCI or PC Card DMA. On the PC Card side, the PCI1031 supports the DMA protocol defined in the

1995 PC Card standard on both sockets. On the PCI side, the PCI1031 supports a distributed DMA protocol,

compliant with the distributed DMA on the PCIWay, revision 6.0, specification. It also supports PC/PCI DMA in

systems designed with the Intel MPIIX.

DMA on PCI is accomplished by compliance with the distributed DMA specification. The PCI1031 complies with

this specification as it applies to DMA devices, and implements two DMA channels; one per socket. Each DMA

channel is controlled by the host via a 16-byte window in PCI I/O address space. This window is mapped in

internal PCI1031 registers that are similar to the 8237 DMA controller programming model. By programming

these registers, the PCI1031 services DMA requests from PC Card applications by initiating PCI bus mastering

cycles to host memory address space.

DMA configuration

Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers.

These registers are found in the PCI configuration header, offsets 94h and 98h (see

test register and socket

DMA register 0). Socket DMA register 0 applies to the PC Card portion of DMA transfers. Socket DMA register 1

applies to the PCI portion of DMA transfers and complies with the distributed DMA specification.

Socket DMA register 0 has only two significant bits. Bits1–0 encode the DREQ signal used by the PC Card. This

field must be programmed with a valid value before the PCI1031 initiates a DMA transfer. Socket DMA register 1

has 16 significant bits, and the encoding is shown in Table 9. The most important field in socket DMA register 1

is the base address that locates the DMA registers in PCI I/O address space. This is how the host communicates

and configures the DMA transfer process.

Table 9. Socket DMA Register 1

BIT

TYPE

FUNCTION

31–16

Reserved. Bits 31–16 are read only and return 0s when read. Writes have no effect.

15–4

R/W

DMA base address. Bits 15–4 locate the socket DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O

address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K bytes of I/O

address space. The lower four bits are hardwired to 0, forcing the window to a natural 16-byte boundary.

Nonlegacy extended addressing. This is not supported on the PCI1031 and always returns a 0.

2–1

R/W

Transfer size. Bits 2–1 specify the width of the DMA transfer on the PCI interface. This field is encoded as:

00 = 8-bit transfer (default)

01 = 16-bit transfer

10 = Reserved

11 = Reserved

R/W

Decode enable. Enables the decoding of the DMA base address by the PCI1031. Bit 0 is encoded as:

0 = Disabled (default)

1 = Enabled

When host software initializes the PCI1031, the base address in socket DMA register 1 can be programmed,

but not enabled. When a particular DMA-capable PC Card is installed in the socket, host software can proceed

to program the DREQ signaling option, the datapath width, and enable the DMA register decode in I/O space.

These options are specific to the PC Card and must be set when the card is configured, but not when the socket

is configured. After setting these options and enabling the DMA register decode, the DMA registers can be

programmed. The DMA register programming model is shown in Table 10.

PCI1031 Datasheet(PDF) 28 Page - Texas Instruments

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