PCI1031 datasheet(14/100 Pages) TI

14 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PCI interface

This section describes the PCI interface of the PCI1031, how the device responds and participates in PCI bus

cycles, and how the major internal registers appear in the PCI address space. The PCI1031 provides all required

signals for PCI master/slave (initiator/target) devices, and can operate in either 5-V or 3.3-V PCI signaling

environments by connecting the two VCCP terminals to the desired switching level.

The PCI1031 is a true multifunction PCI device, with two different PCI functions residing within the device. PCI

function 0 is associated with PC Card socket A and PCI function 1 is associated with PC Card socket B. The

PCI1031 behaves in accordance to the PCI specification for multifunction devices. Functions 0 and 1 have

separately addressable PCI configuration headers, and can use PCI INTA and INTB, respectively.

The PCI1031 responds as a PCI target device to PCI bus cycles based on its decode of the address phase of

each cycle and internal register settings of the device. Table 3 lists the valid PCI bus cycles and their encoding

on the 4-bit C/BE bus during the address phase of a bus cycle. The most common PCI bus commands are read

and write cycles to one of the three PCI address spaces: memory, I/O, and configuration address spaces.

Table 3. PCI Command Definition

C/BE3–C/BE0

COMMAND

0000

Interrupt acknowledge

0001

Special cycle

0010

I/O read

0011

I/O write

0100

Reserved

0101

Reserved

0110

Memory read

0111

Memory write

1000

Reserved

1001

Reserved

1010

Configuration read

1011

Configuration write

1100

Memory read multiple

1101

Dual address cycle

1110

Memory read line

1111

Memory write and invalidate

The PCI1031 never responds as a PCI target device to the interrupt acknowledge, special cycle, dual address

cycle, or reserved commands, nor will it initiate them as a PCI master device. The remaining PCI commands

address one of the three PCI address spaces mentioned earlier, and each is described in the following three

sections. The PCI1031 accepts PCI cycles by asserting DEVSEL as a medium-speed device.

The ability of the PCI1031 to respond to PCI memory or I/O bus cycles is dictated by register bits in the PCI

command register (see

PCI command). This register is located in the PCI configuration header at offset 04h

and is required by the PCI local bus specification. Bits 0 and 1 of this register enable the PCI1031 to respond

to I/O and memory cycles, respectively. Host software must set these bits during initialization of the device. Bit 2

of this register enables/disables the bus-mastering capability of the PCI1031 on the PCI bus. Host software must

also set this bit during device initialization.

PCI1031 Datasheet(PDF) 14 Page - Texas Instruments

PCI1031 Datasheet(HTML) 14 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL