PCI1031 datasheet(72/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ExCA card detect and general control register (index 16h, 56h)

Bit

Name

ExCA card detect and general control

Type

R/W

Default

ExCA card detect and general control

Type:

Read only, write only, read/write (see individual bit descriptions)

Offset:

CardBus socket address + 816h; Card A ExCA offset 16h

Card B ExCA offset 56h

Default:

XX00 0000b

Description: This register controls how the ExCA registers for the socket respond to card removal, as well

as reporting the status of the VS1 and VS2 signals at the PC Card interface. Refer to Table 35

for a complete description of the register contents.

Table 35. ExCA Card Detect and General Control Register (Index 16h, 56h)

BIT

TYPE

FUNCTION

VS2. Bit 7 reports the current state of the VS2 signal at the PC Card interface and does not have a default value. Bit 7

is encoded as:

0 = VS2 is low.

1 = VS2 is high.

VS1. Bit 6 reports the current state of the VS1 signal at the PC Card interface and does not have a default value. Bit 6

is encoded as:

0 = VS1 is low.

1 = VS1 is high.

Software card detect interrupt. If the card detect enable bit in the ExCA card status-change interrupt configuration register

(see

ExCA card status-change interrupt configuration register) is set, writing a 1 to bit 5 causes a card detect card status

change interrupt for the associated card socket. If the card detect enable bit is cleared to 0 in the card status-change

interrupt configuration register, writing a 1 to the software card detect interrupt bit has no effect. Bit 5 is write only. A read

operation of this bit always returns 0. Bit 5 is encoded as:

0 = Software card detect interrupt disabled (default)

1 = Software card detect interrupt enabled

R/W

Card detect resume enable. If bit 4 is set to 1 and a card detect change has been detected on the CD1 and CD2 inputs,

RI_OUT output goes from high to low. The RI_OUT remains low until the card status-change bit in the ExCA card

status-change register (see

ExCA card status-change register) is cleared. If bit 4 is a 0, the card detect resume

functionality is disabled. Bit 4 is encoded as:

0 = Card detect resume disabled (default)

1 = Card detect resume enabled

3–2

Reserved. Bits 3–2 are read only and return 0s when read.

R/W

event. Bit 1 is encoded as:

0 = No change to ExCA registers upon card removal (default)

1 = Reset ExCA registers upon card removal

Reserved. Bit 0 is read only and returns 0 when read.

PCI1031 Datasheet(PDF) 72 Page - Texas Instruments

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