PCI1031 datasheet(30/100 Pages) TI

30 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DMA transfers (continued)

PCI I/O read and write cycles to the DMA registers are accepted and serviced during DMA transfers. If, while

a DMA transfer is in progress, the host resets the DMA channel, the PCI1031 asserts TC and ends the PC Card

cycle(s). TC is indicated in the DMA status register. At the PC Card interface, the PCI1031 supports demand

mode transfers. The PCI1031 asserts DACK the entire duration of the transfer unless DREQ is high

(deasserted) before TC. There is no performance penalty for long wait states during this mode of operation as

there is in the legacy ISA system, because the DMA channel is a dedicated resource localized at the

PC Card socket.

PC/PCI DMA

The PC/PCI DMA protocol provides a way for legacy I/O devices to do DMA transfers on the PCI bus in systems

equipped with the Intel MPIIX. The Intel MPIIX supports PC/PCI DMA expansion for docking station applications

where I/O devices require DMA transfers between the docking station PCI bus or extended I/O bus and a PCI

bus in the notebook docking computer.

In the PC/PCI DMA protocol, the PCI1031 acts as a PCI slave device. The Intel MPIIX DMA controller uses

request/grant pairs, REQ[A–B] and GNT[A–B], which are configured to support a PCI DMA slave device such

as the PCI1031. The Intel MPIIX REQ and GNT pins correspond to the PCI1031 IRQ7 and IRQ11 pins,

respectively. Under the PC/PCI protocol, a PCI DMA slave device requests a DMA transfer using a serialized

protocol on REQ. The Intel MPIIX, as a bus master, arbitrates for the PCI bus. When the Intel MPIIX gets control

of the PCI bus, it asserts GNT on the PCI1031 and, for the selected DMA channel, runs the DMA I/O cycles and

memory cycles on the PCI bus.

PC/PCI DMA is enabled for each PC Card16 slot by setting bit 19 in the respective system control register (see

Table 16). On power up, bit 19 is cleared, disabling PC/PCI DMA. Bit 3 of each PCI1031 system control register

is a global PC/PCI enable bit. When bit 3 is set, the PCI1031 can request a DMA transfer by asserting IRQ7

(REQ) and encoding the channel request information using the serialized protocol. When the Intel MPIIX gets

control of the PCI bus, it encodes the granted channel on the PCI1031 IRQ11 (GNT) pin. On power up, bit 3

is cleared and PC/PCI DMA is disabled. When the PCI1031 receives a GNT signal, it looks at the DMA I/O

address to determine the type of transfer. The cycle types are as follows:

DMA I/O ADDRESS

DMA CYCLE TYPE

TERMINAL COUNT

PCI CYCLE TYPE

00h

Normal

I/O read/write

04h

Normal TC

I/O read/write

C0h

Verify

I/O read

C4h

Verify TC

I/O read

PCI1031 Datasheet(PDF) 30 Page - Texas Instruments

PCI1031 Datasheet(HTML) 30 Page - Texas Instruments

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