PCI1031 datasheet(40/100 Pages) TI

40 / 100 page

PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 14. PCI Status Register

BIT

TYPE

FUNCTION

R/W

Parity error status

0 = PCI1031 does not detect a parity error (default).

1 = PCI1031 detects a parity error.

R/W

System error status

0 = PCI1031 does not generate a system error on the SERR line (default).

1 = PCI1031 generates a system error on the SERR line.

R/W

Initiator abort status

0 = A bus initiator abort does not terminate a bus initiator’s transaction (default).

1 = A bus initiator abort terminates a bus initiator’s transaction.

R/W

Target abort status. A target abort terminates a PCI1031 bus master transaction.

0 = A target abort does not terminate a PCI1031 bus master transaction (default).

1 = A target abort terminates a bus master transaction.

R/W

Target abort status. The PCI1031 target abort terminates a bus master transaction.

0 = A PCI1031 target abort does not terminate a bus master transaction (default).

1 = A PCI1031 target abort terminates a bus master transaction.

10–9

Device select timing status. Bits 10–9 are encoded with the DEVSEL timing. These read-only bits are hardwired as 01b,

indicating a medium-speed device.

R/W

Data parity status

0 = No data parity errors occur (default).

1 = Data parity errors occur; the following conditions are met:

a. PERR is asserted by the bus initiator or the bus initiator observed PERR asserted.

b. The agent that set the bit is the bus initiator during the transaction when the error occurred.

c. Parity error response (bit 6 in the command register) is enabled.

Fast back-to-back capable. The PCI1031 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0.

User-definable feature (UDF) support. The PCI1031 does not support the UDF option; therefore, bit 6 is hardwired to 0.

66 MHz capable. The PCI1031 operates at a maximum frequency of 33 MHz; therefore, bit 5 is hardwired to 0.

4–0

Reserved. Bits 4–0 are read only alnd return 0s when read. Writes have no effect.

PCI revision ID register

Bit

Name

PCI revision ID

Type

Default

PCI revision ID

Type:

Read only

Offset:

08h

Default:

02h

Description: The PCI revision ID register is selected by TI and indicates the silicon revision.

PCI1031 Datasheet(PDF) 40 Page - Texas Instruments

PCI1031 Datasheet(HTML) 40 Page - Texas Instruments

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