PCI1031 datasheet(16/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PCI I/O address space

The PCI local bus specification defines an I/O address space accessed using 32-bit addresses, yielding a

4G-byte usable address space. The PCI1031 decodes PCI I/O cycles as a PCI target device only if host software

has enabled it to do so (see bit 0 of the

PCI command register). If so enabled, the PCI1031 positively decodes

the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed I/O window.

Such a window can be mapped either to internal PCI1031 registers or to PC Card address space.

There are two instances where the PCI1031 maps internal registers to PCI I/O address space. The first is the

legacy 16-bit PC Card index/data registers (used to access the ExCA registers), and the second is DMA socket

registers (used to access registers in distributed DMA). In both cases, the locations of these windows are

programmed by base address registers in PCI configuration space. The legacy 16-bit PC Card base address

(see

PC Card 16-bit I/F legacy-mode base address) is located at configuration offset 44h, and is common to

both PCI1031 functions 0 and 1. This base address locates a 2-byte window in I/O space anywhere in the 32-bit

I/O address space. The socket DMA base address register (see

socket DMA register 1) is located at

configuration offset 98h, and is separate and distinct for functions 0 and 1. This base address locates a 16-byte

window in I/O space in the lower 64K bytes of PCI I/O address space. For a complete description of this base

address register and the socket DMA registers, see

socket DMA register 1 and DMA registers.

The PCI1031 provides the ability for host software to program PCI I/O windows to PC Card address spaces.

These windows provide the bounds upon which the PCI1031 positively decodes I/O cycles from PCI to a

PC Card, and are the primary means for applications to communicate with PC Cards. See

16-bit PC Cards and

windows, ExCA registers, and CardBus PC Cards and windows.

PCI memory address space

The PCI local bus specification also defines a memory address space accessed using 32-bit addresses, yielding

a 4G-byte usable address space. The PCI1031 decodes PCI memory cycles as a PCI target device only if host

software has enabled it to do so (see bit 1 of the

PCI command register). If so enabled, the PCI1031 positively

decodes the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed

memory window. Such a window can be mapped either to internal PCI1031 registers or to PC Card

address space.

The only case where the PCI1031 maps internal registers to PCI memory address space is the CardBus/ExCA

registers that are mapped into a 4K-byte window for each socket. The location of these windows is programmed

by a base address register in PCI configuration space. The CardBus socket/ExCA base address (see

CardBus

socket registers/ExCA registers base address register) is located at configuration offset 10h and is separate

and distinct from functions 0 and 1. Each base address locates a 4K-byte window in memory space anywhere

in the 32-bit memory address space. For a description of this base address register and the CardBus socket

registers, see

CardBus socket registers/ExCA registers base address register.

The PCI1031 enables host software to program PCI memory windows to PC Card address spaces. These

windows provide the bounds on which the PCI1031 positively decodes memory cycles from PCI to a PC Card

and are the primary means for applications to communicate with PC Cards (see

16-bit PC Cards and windows

and

ExCA registers). A memory read always disconnects after the first data phase.

compliance to PCI local bus specification revision 2.1

The most significant additions to the PCI local bus specification revision 2.1 are the latency requirements on

PCI peripherals. Minimum response times are specified for a PCI device to respond with valid data. These

requirements are intended to improve throughput and reduce latencies on the PCI bus. The PCI1031 is fully

compliant with these guidelines.

Other additions to revision 2.1 of the PCI local bus specification include the subsystem ID and subsystem vendor

ID registers in the PCI configuration header.

PCI1031 Datasheet(PDF) 16 Page - Texas Instruments

PCI1031 Datasheet(HTML) 16 Page - Texas Instruments

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