PCI1031 datasheet(83/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

test register (reserved)

Bit

Name

Test

Type

R/W

Default

Bit

Name

Test

Type

R/W

Default

Test

Type:

Read only, write only, nonfunctional (see individual bit descriptions)

Offset:

CardBus socket address + 20h

Default:

0000h

Size:

Four bytes

Description: This register provides control over power management for the socket. It provides a

mechanism for slowing or stopping the clock on the card interface when the card is idle. Refer

to Table 43 for a complete description of the register contents.

Table 43. Test Register

BIT

TYPE

FUNCTION

31–26

Reserved. Bits 31–26 are read only and return 0s when read.

Socket access status (nonfunctional)

Socket mode status bit (nonfunctional)

23–17

Reserved. Bits 23–17 are read only and return 0s when read.

R/W

CardBus PC Card clock control enable bit (nonfunctional)

15–1

Reserved. Bits 15–1 are read only and return 0s when read.

R/W

CardBus PC Card clock control bit (nonfunctional)

DMA registers

The DMA base address register, located in PCI configuration space at offset 98h (see

socket DMA register 0),

points to a 16-byte region in PCI I/O space where the DMA registers reside. The names and locations of these

registers are summarized in Table 44. These registers are identical in function, but different in location, to the

8237 DMA controller. The similarity between the register models retains some level of compatibility with legacy

DMA and simplifies the translation required by the master DMA device when forwarding legacy DMA writes to

DMA channels.

While the DMA register definitions are identical to those in the 8237 DMA controller, some register bits defined

in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1031

implements these obsolete register bits as read-only nonfunctional bits. The reserved registers shown in

Table 44 are implemented as read only, and return 0s when read. Writes to reserved registers have no effect.

PCI1031 Datasheet(PDF) 83 Page - Texas Instruments

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