PCI1031 datasheet(18/100 Pages) TI

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PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT

SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PC Card insertion/removal and recognition (continued)

Based on the information described in Table 4, the PCI1031 executes an algorithm upon card insertion that

alternatively drives the VS1 and VS2 pins to low and high levels to determine which of the card types has been

inserted. This process is completed without VCC ever being applied to the socket. Once the PCI1031 has

successfully determined the card type and voltage requirements, it updates the appropriate status bits in the

socket present state register (see

socket present state register) and asserts a CSC interrupt to the host system.

Host software must then read the CardBus socket registers to determine the card type and voltage requirements

and respond accordingly.

16-bit PC Cards and windows

The PCMCIA revision 1.0 defined the original 16-bit memory card, and the later PCMCIA revisions 2.0 and 2.1

defined the 16-bit I/O card. Both types of 16-bit PC Cards have the 16-bit datapaths and a 26-bit address bus

defined. Status and control signals differ between the two card types. The PCI1031 fully supports both types

of cards. The ExCA register set is implemented in the PCI1031, which provides the industry standard Intel

82365SL-DF programming model.

The 16-bit memory cards can have two types of memory address space: attribute memory and common

memory. The attribute memory address space contains the CIS, and common memory is the memory space

used by the application. The CIS is defined by PCMCIA and contains a variety of information about the card

capabilities and resource requirements. Host software reads and parses the CIS to set up the system resources

to use the card application. Both attribute and common memory are accessed with 26-bit addresses, resulting

in a total addressable memory address space of 64M bytes.

The 16-bit I/O cards can possess attribute and common memory, but also have an I/O address space. This

address space is accessed via 16-bit I/O addresses, resulting in a 64K-byte I/O address space.

The PCI1031 provides a windowing mechanism to link the PCI address space to 16-bit PC Card address space.

Both of these memory and I/O windows are programmed by host software in the ExCA registers. The PCI1031

provides up to five memory windows per socket and two I/O windows per socket. Once enabled, the PCI1031

positively decodes and claims bus cycles that fall within these windows. Bus cycles to the PC Card are then

initiated to write data to the card (in the case of a PCI write cycle) or to read data from the card (in the case of

a PCI read cycle).

Memory and I/O windows to 16-bit PC Cards have several programmable options associated with them. Host

software can choose among these options by setting the appropriate bits in the appropriate ExCA registers.

These options include:

D Window start address

D Window end address

D Window offset address

D Page address (for 16-bit PC Card memory windows only)

D Attribute or common memory access (for 16-bit PC Card memory windows only)

D PC Card datapath width (8 bit or 16 bit)

D Wait state timing (ISA bus timing or minimum)

D Write protection (enable/disable writes to memory windows)

The start, end, offset, and page address define the bounds of the memory window in PCI and PC Card memory

address spaces. The page address is necessary to take into account the difference in addressable memory

between PCI (4G bytes) and 16-bit PC Cards (64M bytes). The 8-bit page address appended to the 26-bit start

and end addresses define the bounds of the window in PCI memory address space. When a PCI memory cycle

is decoded and claimed, the PCI1031 adds the offset address to the PCI address before passing the lower 26

bits to the PC Card. The memory windows need not be aligned between the two address spaces.

PCI1031 Datasheet(PDF) 18 Page - Texas Instruments

PCI1031 Datasheet(HTML) 18 Page - Texas Instruments

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