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DA6021 Datasheet(PDF) 204 Page - Renesas Technology Corp

Part # DA6021
Description  HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR
PDF  225 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA6021 Datasheet(HTML) 204 Page - Renesas Technology Corp

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DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
204 of 224
www.dialog-semiconductor.com
23. Debug Ports
There are 2 debug ports foreseen, one for the SVID and another one for the I2C interface
SVID Debug port
23.1
The intent is to disable PMIC SVID buffers connected to the SOC/CPU when in debug mode and redirect
communication to an external bus master using a secondary set of pins. This will enable external control of the
PMIC interface without SOC/CPU bus contention. In addition, the debug channel enables a point to point bus
topology with the external bus master, thereby providing clean signal integrity. The DEBUG_CS signal is used to
disable SOC SVID transmission during debug. This will ensure the SOC does not hang awaiting PMIC SVID
responses.
A diagram, truth table, and brief write up are provided below.
Figure 74: SVID Debug Port Bus Diagram
External Channel 0 (Debug)
External Channel 1 (SOC)
DEBUG_CS
DEBUG_SVID
_CLK
DEBUG_SVID
_DATA
DEBUG_SVID
_ALERT#
SVID_CLK
SVID_DATA
SVID_ALERT#
“H” (VSYS)
CLK
DATA
ALERT#
Disabled
Disabled
Disabled
“L” (0V)
Disabled
Disabled
Disabled
CLK
DATA
ALERT#
Table 112: SVID Debug Port Truth Table
PMIC SVID CONTROL BLOCK
SVID DEBUG PORT
SOC SVID CONTROL
External Channel 0
External Channel 1
Internal Channel
PMIC
PLATFORM
VSYS
DEBUG_CS



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