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TMS320F Datasheet(PDF) 31 Page - Texas Instruments |
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TMS320F Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 389 page ![]() Central Processing Unit 2-8 2.4 Central Processing Unit The ’C24x is based on TI’s ’C2xx CPU. It contains: - A 32-bit central arithmetic logic unit (CALU) - A 32-bit accumulator - Input and output data-scaling shifters for the CALU - A 16-bit × 16-bit multiplier - A product-scaling shifter - Data-address generation logic, which includes eight auxiliary registers and an auxiliary register arithmetic unit (ARAU) - Program-address generation logic 2.4.1 Central Arithmetic Logic Unit (CALU) and Accumulator The ’C24x performs 2s-complement arithmetic using the 32-bit CALU. The CALU uses 16-bit words taken from data memory, derived from an immediate instruction, or from the 32-bit multiplier result. In addition to arithmetic opera- tions, the CALU can perform Boolean operations. The accumulator stores the output from the CALU; it can also provide a second input to the CALU. The accumulator is 32 bits wide and is divided into a high- order word (bits 31 through 16) and a low-order word (bits 15 through 0). Assembly language instructions are provided for storing the high- and low- order accumulator words to data memory. 2.4.2 Scaling Shifters The ’C24x has three 32-bit shifters that allow for scaling, bit extraction, extended arithmetic, and overflow-prevention operations: - Input data-scaling shifter (input shifter). This shifter left-shifts 16-bit in- put data by 0 to 16 bits to align the data to the 32-bit input of the CALU. - Output data-scaling shifter (output shifter). This shifter left-shift output from the accumulator by 0 to 7 bits before the output is stored to data memory. The content of the accumulator remains unchanged. - Product-scaling shifter (product shifter). The product register (PREG) receives the output of the multiplier. The product shifter shifts the output of the PREG before that output is sent to the input of the CALU. The prod- uct shifter has four product shift modes (no shift, left shift by one bit, left shift by four bits, and right shift by six bits), which are useful for performing multiply/accumulate operations, performing fractional arithmetic, or justi- fying fractional products. |
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